Verilog Code

Discussion in 'VHDL' started by dcell, Nov 21, 2004.

  1. dcell

    dcell Guest

    Could anyone look at my code here and tell me what the HELL is wrong
    with it?

    I keep getting an error complaining about endmodule. I'm about ready
    to destroy something.

    Thanks.

    module barrel(data_in, shift, data_out) ;
    input [3:0]data_in;
    input [1:0]shift;
    output [3:0]data_out;
    reg [3:0]data_out;

    always@(data_in or shift)

    case(shift)
    0: data_out <= data_in ;
    1: data_out <= data_in*2 ;
    2: data_out <= data_in*4 ;
    3: data_out <= data_in*8 ;

    endmodule
    dcell, Nov 21, 2004
    #1
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  2. dcell

    Uwe Bonnes Guest

    dcell <> wrote:
    : Could anyone look at my code here and tell me what the HELL is wrong
    : with it?

    : I keep getting an error complaining about endmodule. I'm about ready
    : to destroy something.

    : Thanks.

    : module barrel(data_in, shift, data_out) ;
    : input [3:0]data_in;
    : input [1:0]shift;
    : output [3:0]data_out;
    : reg [3:0]data_out;

    : always@(data_in or shift)

    : case(shift)
    : 0: data_out <= data_in ;
    : 1: data_out <= data_in*2 ;
    : 2: data_out <= data_in*4 ;
    : 3: data_out <= data_in*8 ;

    : endmodule

    You're missing the 'endcase' statement

    Bye
    --
    Uwe Bonnes -darmstadt.de

    Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
    --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
    Uwe Bonnes, Nov 21, 2004
    #2
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