verilog module instantantiation in VHDL top level

[praveen.kantharajapura]

Hi all,

In my design all the modules are in VHDL except one which is in
verilog.I wanted to know if it is possible to call my verilog module in
my VHDL top level.

If possible can any body tell me how to go about it.

Regards,
Praveen

 

[Tarun Batra]

Hi all,

In my design all the modules are in VHDL except one which is in
verilog.I wanted to know if it is possible to call my verilog module in
my VHDL top level.

If possible can any body tell me how to go about it.

Regards,
Praveen

Hi Praveen,
You will have to create a wrapper for the Verilog model as:

Entity <module name> is
End <module name>;

architecture verilog of <name> is
attribute foreign of verilog:architecture is "VERILOG(event)
work.<module name>:modulel";
begin
end;

In case you are using NCSIM, you can directly instantiate the verilog
component in VHDL.
NCSIM allows the instantiation of the Verilog in VHDL either through
direct instantiation, component binding or default bindings.

-Tarun