Verilog / Simulink Cosimulation??

Discussion in 'VHDL' started by vex_helix, Oct 14, 2007.

  1. vex_helix

    vex_helix

    Joined:
    Oct 14, 2007
    Messages:
    4
    Hi,

    I designed a Viterbi decoder in Verilog and need a testbench to verify its functionality. I really don't want to create testbenches in verilog. I read about the link for modelsim for matlab/simulink but will that be sufficient to check funtionality and find BER (is it a true verification? Can I trust the results)? This is what I am trying to do: (binary generator->encoder->modulator->AWGN->demodulator-> [Verilog decoder] -> [Tx/Rx BER calculator]->display)

    Thx,
    Gantt
     
    vex_helix, Oct 14, 2007
    #1
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