verilog strength equivalent in vhdl

Discussion in 'VHDL' started by saqman_1947@hotmail.com, Mar 13, 2007.

  1. Guest

    I have a top level in vhdl (top_vhdl) that instantiates two verilog
    module (a_verilog and b_verilog). I need to pass a signal from
    "a_verilog"to "b_verilog" throuhg "top_vhdl". Problem is that this
    signal can have any of the verilog signal strength "pull0, pull1,
    weak0, weak1" while vhdl translates "pull0 and weak0" to "L" and
    "pull1 and weak1" to "H".
    Anyone knows how to go around it ??
    Thanks
     
    , Mar 13, 2007
    #1
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  2. schrieb:

    > I have a top level in vhdl (top_vhdl) that instantiates two verilog
    > module (a_verilog and b_verilog). I need to pass a signal from
    > "a_verilog"to "b_verilog" throuhg "top_vhdl". Problem is that this
    > signal can have any of the verilog signal strength "pull0, pull1,
    > weak0, weak1" while vhdl translates "pull0 and weak0" to "L" and
    > "pull1 and weak1" to "H".
    > Anyone knows how to go around it ??


    What about a Verilog container around that two Verilog modules?

    Ralf
     
    Ralf Hildebrandt, Mar 13, 2007
    #2
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