verilog testbench fot vhdl ams

Discussion in 'VHDL' started by apurva, Feb 6, 2007.

  1. apurva

    apurva Guest

    hi all,

    i want to use the signal values used in RTL verilog testbench to drive
    the signals in my vhdl-ams model.
    how ca i do this in advanced ms?

    can anyone please help?

    regards
    apurva
     
    apurva, Feb 6, 2007
    #1
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  2. On Feb 6, 6:59 pm, "apurva" <> wrote:
    > hi all,
    >
    > i want to use the signal values used in RTL verilog testbench to drive
    > the signals in my vhdl-ams model.
    > how ca i do this in advanced ms?
    >
    > can anyone please help?
    >
    > regards
    > apurva


    If your simulator supports mixed mode simulation, this should be
    straight forward. If not you will need to rewrite Verilog TB to VHDL
    which shouldn't be that hard either.

    Regards
    Ajeetha, CVC
    www.noveldv.com
     
    Ajeetha (www.noveldv.com), Feb 6, 2007
    #2
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