Verilog/VHDL Simulation

Discussion in 'VHDL' started by Elf, Oct 10, 2003.

  1. Elf

    Elf Guest

    Hi,

    Can anyone tell me if the netlist generated by a simulator is language
    specific or not...
    like for eg. I generate code for the "same design" in both Verilog and
    in VHDL and then simulate them using a single simulator, will the
    netlist thats generated be the same..?
    One may say Yes, coz ultimately what the simulator is doing is
    generating "assembly language instructions" based on the design code,
    so they shd be independent of the HDL....

    But then I have seen studies where the code for similar Verilog and
    VHDL designs had different number of code lines, and differnt no. of
    "partitions(always block/process block)...and this might result in a
    slightly diffenrt netlist being generated....

    regards,
    Elf.
    Elf, Oct 10, 2003
    #1
    1. Advertising

  2. Elf wrote:

    > Can anyone tell me if the netlist generated by a simulator is language
    > specific or not...


    Synthesis generates a netlist.
    Simulation generates a binary version of the source code
    optimized for speed.

    I would be surprised if either were identical for
    vhdl and verilog versions of the same design.
    The best way to answer this question is to
    try it for a simple example.

    -- Mike Treseler
    Mike Treseler, Oct 10, 2003
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Andy Botterill

    VHDL/Verilog simulation problem

    Andy Botterill, Nov 4, 2003, in forum: VHDL
    Replies:
    0
    Views:
    1,454
    Andy Botterill
    Nov 4, 2003
  2. absr
    Replies:
    2
    Views:
    1,683
    flyfish866
    Dec 24, 2007
  3. Mirza
    Replies:
    11
    Views:
    2,064
    Paul Uiterlinden
    Jul 21, 2007
  4. kartikey
    Replies:
    0
    Views:
    1,560
    kartikey
    Dec 18, 2007
  5. alb

    vhdl & verilog simulation

    alb, Sep 9, 2013, in forum: VHDL
    Replies:
    4
    Views:
    327
Loading...

Share This Page