Verilog / VHDL

Discussion in 'VHDL' started by EdwardH, Dec 18, 2003.

  1. EdwardH

    EdwardH Guest

    Hi

    I am an experienced Verilog designer and am about to start
    work with a company that uses VHDL. I have been studying VHDL
    and am starting to get a feel for the language. It would be good however to
    be able to relate features of Verilog with equivalents in VHDL.

    A specific question relates to compiler directives and command
    line arguments in Verilog i.e. 'ifdef and +define+
    The application is for a testbench where I want to write code to print
    specific information for debug which I don't want to be printed
    when the testbench executes normally. e.g. in Verilog I can write
    code such as:

    'ifdef debug_mode
    code to print lots of debug information
    'endif

    There can be many of these code segments throughout the testbench
    and if I want to turn them on, in the compile script I would have:

    +define+debug_mode

    Is there an equivalent mechanism in VHDL?

    Does any body know of documents that discuss such language
    equivalents?

    Thanks in advance, Edward
    EdwardH, Dec 18, 2003
    #1
    1. Advertising

  2. EdwardH wrote:
    >
    > Hi
    >
    > I am an experienced Verilog designer and am about to start
    > work with a company that uses VHDL. I have been studying VHDL
    > and am starting to get a feel for the language. It would be good however to
    > be able to relate features of Verilog with equivalents in VHDL.
    >
    > A specific question relates to compiler directives and command
    > line arguments in Verilog i.e. 'ifdef and +define+
    > The application is for a testbench where I want to write code to print
    > specific information for debug which I don't want to be printed
    > when the testbench executes normally. e.g. in Verilog I can write
    > code such as:
    >
    > 'ifdef debug_mode
    > code to print lots of debug information
    > 'endif
    >
    > There can be many of these code segments throughout the testbench
    > and if I want to turn them on, in the compile script I would have:
    >
    > +define+debug_mode
    >
    > Is there an equivalent mechanism in VHDL?
    >
    > Does any body know of documents that discuss such language
    > equivalents?
    >
    > Thanks in advance, Edward


    I would do a similar thing using generics,
    as in this very reduced example:


    entity test is

    generic (debug : boolean := false); -- default

    end test;

    architecture single of test is

    begin

    single : process

    begin

    assert not(debug)
    report "Debug Message"
    severity note;

    wait ; -- halt;

    end process;

    end single;

    And then, overriding the value for the generic
    when necessary, e.g for ModelSim:

    vsim -Gdebug=true work.test

    HTH,
    Fran.
    Francisco Camarero, Dec 18, 2003
    #2
    1. Advertising

  3. Francisco Camarero <"camarero a"@t ee [d.ot] ethz [do.t] ch> writes:

    > EdwardH wrote:

    [How to do the equivalent of '+define+debug_mode' in VHDL]:
    > > There can be many of these code segments throughout the testbench
    > > and if I want to turn them on, in the compile script I would have:
    > >
    > > +define+debug_mode
    > >
    > > Is there an equivalent mechanism in VHDL?
    > >
    > > Does any body know of documents that discuss such language
    > > equivalents?

    >
    > I would do a similar thing using generics,
    > as in this very reduced example:


    [snip example]

    Another approach is to have a signal on the top level of your
    testbench, which you manipulate using Tcl (e.g. "force -deposit
    /debug_mode true").

    Or even have a (text) file parser in VHDL directly, which assigns a
    value to the signal in question, based on keywords in the text file.

    Regards,


    Kai
    Kai Harrekilde-Petersen, Dec 18, 2003
    #3
  4. Hi,
    I use frequently the if-generate construct:

    architecture HelloWorld of HelloWorld is
    constant DEBUG : BOOLEAN := TRUE;
    begin

    GEN1:
    if(DEBUG=TRUE) generate
    assert (A=B) report "Error: It is not equal.";
    end generate;

    end HelloWorld;

    Best Regards,
    Slawek Grabowski

    "Kai Harrekilde-Petersen" <> wrote in message
    news:...
    > Francisco Camarero <"camarero a"@t ee [d.ot] ethz [do.t] ch> writes:
    >
    > > EdwardH wrote:

    > [How to do the equivalent of '+define+debug_mode' in VHDL]:
    > > > There can be many of these code segments throughout the testbench
    > > > and if I want to turn them on, in the compile script I would have:
    > > >
    > > > +define+debug_mode
    > > >
    > > > Is there an equivalent mechanism in VHDL?
    > > >
    > > > Does any body know of documents that discuss such language
    > > > equivalents?

    > >
    > > I would do a similar thing using generics,
    > > as in this very reduced example:

    >
    > [snip example]
    >
    > Another approach is to have a signal on the top level of your
    > testbench, which you manipulate using Tcl (e.g. "force -deposit
    > /debug_mode true").
    >
    > Or even have a (text) file parser in VHDL directly, which assigns a
    > value to the signal in question, based on keywords in the text file.
    >
    > Regards,
    >
    >
    > Kai
    Slawek Grabowski, Dec 22, 2003
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    0
    Views:
    8,693
    walala
    Aug 1, 2003
  2. walala
    Replies:
    3
    Views:
    5,666
    walala
    Aug 30, 2003
  3. shumon
    Replies:
    1
    Views:
    11,778
    Jim Wu
    Sep 24, 2003
  4. Elf

    Verilog/VHDL Simulation

    Elf, Oct 10, 2003, in forum: VHDL
    Replies:
    1
    Views:
    690
    Mike Treseler
    Oct 10, 2003
  5. afd
    Replies:
    1
    Views:
    8,324
    Colin Paul Gloster
    Mar 23, 2007
Loading...

Share This Page