VHDL-200x and Object-Oriented Hardware design

[Amal]

Verilog2001 and SystemVerilog introduced the notion of a class and
objects for describing hardware and/or for verification perposes. I
have not seen any activities on the VHDL-200x-FT for adding these
features (or have I missed it?). I know of the addition of package and
subprogram generics (DTA) and also allowing composites (arrays and
records) with unconstraint arrays (FT14).

The current proposals allow for abstraction of data types and creating
more generic packages, types, functions. Any thought on the other
aspects of OO in HDL?

My question is: "Are there any proposals or work on adding
object-oriented features to VHDL?"

Seems HDLs, like the EDA tools don't catch up and go as fast as
software/compiler technologies! It's a pitty...

-- Amal

 

[Mike Treseler]

Seems HDLs, like the EDA tools don't catch up and go as fast as
software/compiler technologies! It's a pitty...

More's the pity that few designers
use the facilities for variables,
functions, and procedures that
already exist and work well.

-- Mike Treseler

 

[Duane Clark]

More's the pity that few designers
use the facilities for variables,
functions, and procedures that
already exist and work well.

Okay,okay...

I had been using procedures in testbenches for awhile, but only recently
started using them in designs at your instigation. I must say, they came
in quite handy.

Maybe it is good that you keep bugging people about it

 

[Amal]

Okay,okay...

I had been using procedures in testbenches for awhile, but only recently
started using them in designs at your instigation. I must say, they came
in quite handy.

Maybe it is good that you keep bugging people about it

I have been using packages, procedures and functions as much as I can,
and I can see the missing features and it bothers me that we should
just be content with the language (that is a great one by the way) and
not improeve it.

I was just looking for OO proposals for VHDL-200x, anyone knows of any
proposals?

-- Amal

 

[Mike Treseler]

I was just looking for OO proposals for VHDL-200x, anyone knows of any
proposals?

Have a look here:

http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl

-- Mike Treseler

 

[Jeremy Ralph]

The ability to create a class hierarchy in synthesizable HDL would be
nice. Seems HDLs could tame complexity and improve code re-use with
inheritance. It's a shame VHDL hasn't borrowed the notion of 'derived'
types to enable inheritance like in ADA.

Anyone know if SystemVerilog's object-orientation features are
synthesizable? If not, when?

 

[Martin Thompson]

Seems HDLs, like the EDA tools don't catch up and go as fast as
software/compiler technologies! It's a pitty...

I wouldn't say software technologies are ahead all the time.

EG:

* There's not much in the way of tools that will tell me that my
software is guaranteed to meet my timing deadlines under all
conditions. The timing analyser guarantees my hardware will meet
timing contraints.

* Concurrency is not well handled in most widely-used software
languages. HDLs support it quite nicely.

IMHO of course!

Martin

 

[Andy]

Surely, Brother Treseler, thou speakest the truth! Amen!

There are too many folks writing netlists in VHDL, and calling it a
VHDL design.

Andy Jones

 

[Amal]

I agree and it is true that VHDL is great as it is and not everybody
writes good code or uses the features available now in VHDL. I think I
use VHDL to the extent that I feel it has many shortcomings. Some are
being addressed by Accellera, but I think OO would be a great addition
to the language.

-- Amal

 

[Mike Treseler]

I think I
use VHDL to the extent that I feel it has many shortcomings. Some are
being addressed by Accellera, but I think OO would be a great addition
to the language.

I agree, but I've got work to do.
The vhdl'93 revision started in 1987,
took 6 years to write and about
another 6 years to roll out into FPGA tools.

-- Mike Treseler

 

[Andy]

Amal,

I did not mean to imply that VHDL does not need the improvements you
spoke of; it certainly does. I just agree that it is a pity that the
majority of vhdl-for-synthesis users treat it like a giant netlist,
with gates and registers neatly carved out, rather than using the power
(and unambiguity) of VHDL to create more behavioral, cycle accurate
descriptions, and let the synthesis retiming and other optimizations go
to work on it.

Andy

 

[Jim Lewis]

Hi,
The work started by IEEE has been migrated to Accellera
due to funding issues. Basically we can't get adequate
technical editing for free.

In IEEE VHDL WG plans and Accellera VHDL TC plans OO
is a high priority item, however, it was too much to
complete for this release which is due to be approved
by Accellera board at DAC in July of 2006 - IEEE balloting
will follow later. This will give vendors and users a
chance to try out the features before they get cast in
stone in the IEEE version of the specification.

I would expect the release after the 2006 release to have
OO, constrained random, and interface features. Accellera
tends to do things aligned with DAC, so I would guess that
this would mean DAC 2007.

Alot of you seem to have interest in VHDL - you should join
the Accellera VHDL TC. You can join as a non-member and
get access to technical committee documents and participate
in group activities. Most of the decisions are made at the
subgroup level, where all participants have a vote - contentious
issues get resolved at the TC level with a membership (paying)
vote. I would encourage those of you from larger organizations
to join Accellera and help fund VHDL through the future.

The starting point for the Accellera VHDL TC is here:
http://www.accellera.org/activities/vhdl/

Cheers,
Jim Lewis
IEEE VASG Chair
http://www.vhdl.org/vasg
(vhdl.org = eda.org, except it is currently working)
--
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Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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