VHDL-200x fixed point package takes very long to synthesize

[janbeck]

Hi all, I need some help, if anyone has the time to explain what I am
doing wrong

I am trying to use the fixed point package fixed_pkg and am having
trouble with synthesis

I have a process with just a few lines of code that seems to need
forever to map - it wont finish even over night on a 3Ghz machine.

I am using Synplify Pro with Xilinx ISE.

I have removed all the code lines from the process that do not seem to
make a difference with this problem.

Here is the code snippet that causes me trouble (all variables are
declared like):
shared variable m1: sfixed (32 downto -32) := to_sfixed (50, 32, -32);

process(src_clk_1)
begin
if (src_clk_1'event and src_clk_1='1') then
ykm2 := ykm1;
ykm1 := yk;
yk := to_sfixed (arg => to_integer(unsigned(val1)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
uk := to_sfixed (arg => to_integer(unsigned(val2)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
m1 := resize(ykm2*p11, m1'high,m1'low);
m2 := resize(ykm1*p21, m2'high,m2'low);
m3 := resize(uk*p31, m3'high,m3'low);
m4 := resize(m1+m2, m4'high,m4'low);
t1 := resize(m3+m4, t1'high,t1'low);
m1 := resize(t1*t1, m1'high,m1'low);
p11 := resize(p11 - m1, p11'high,p11'low);
end process;

Any insight or pointers would be appreciated


JAn

 

[Mike Treseler]

I am trying to use the fixed point package fixed_pkg and am having
trouble with synthesis

Simulation is OK?

shared variable m1: sfixed (32 downto -32) := to_sfixed (50, 32, -32);

This is likely your problem.
Shared variables are not commonly supported for synthesis.
Alternatives include
1.regular variables, which can be shared
across procedures in a single process or
2.signals which can be driven across processes.

-- Mike Treseler

 

[janbeck]

Hi!
Thank you for your reply.

I need to move this into hardware, so simulation is not sufficient. I
have actually had everything declared as signals and assigned the
signals in a state machine before. I felt the signals might be the
problem, so I went to the variables, but no luck.

Any other ideas?

Thanks,

JAn

 

[Mike Treseler]

Thank you for your reply.

You are welcome.

I need to move this into hardware, so simulation is not sufficient.

Simulation is sufficient with the right design rules.
And it is necessary in any case, to find logical errors in all
but the most trivial of digital designs.

I have actually had everything declared as signals and assigned the
signals in a state machine before. I felt the signals might be the
problem, so I went to the variables, but no luck.

Any other ideas?

It may be a logical problem.

-- Mike Treseler

 

[David Bishop]

Hi all, I need some help, if anyone has the time to explain what I am
doing wrong

I am trying to use the fixed point package fixed_pkg and am having
trouble with synthesis

I have a process with just a few lines of code that seems to need
forever to map - it wont finish even over night on a 3Ghz machine.

I am using Synplify Pro with Xilinx ISE.

My test case for the fixed point packages uses Synplify Pro.

I have removed all the code lines from the process that do not seem to
make a difference with this problem.

Here is the code snippet that causes me trouble (all variables are
declared like):
shared variable m1: sfixed (32 downto -32) := to_sfixed (50, 32, -32);

Yipe! a 64 bit shared variable! Sure you need it that big?
How about just a variable? Or better yet a signal.
This will synthesize, but I doubt it would run at more tha 0.7 MHz.

process(src_clk_1)
begin
if (src_clk_1'event and src_clk_1='1') then
ykm2 := ykm1;
ykm1 := yk;
yk := to_sfixed (arg => to_integer(unsigned(val1)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
uk := to_sfixed (arg => to_integer(unsigned(val2)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);

Filled with lots of zeros

m1 := resize(ykm2*p11, m1'high,m1'low);
m2 := resize(ykm1*p21, m2'high,m2'low);
m3 := resize(uk*p31, m3'high,m3'low);

64 bit multiply (3 of them), producing a 128 bit result which needs to
be cut down. This is a lot of 18x18 multiplier blocks.

m4 := resize(m1+m2, m4'high,m4'low);
t1 := resize(m3+m4, t1'high,t1'low);

Two 64 bit adders.

m1 := resize(t1*t1, m1'high,m1'low);

Another multiply

p11 := resize(p11 - m1, p11'high,p11'low);
end process;

Any insight or pointers would be appreciated

1) cut down the size of your variables. 64 bits is a great deal of
precision that is probably what is slowing down Synplify.
2) If you are going to resize to 64 bits after every operation, then
a multiply with two 32 bit inputs will work as well and make much less
logic.