VHDL-200x Fixed_pkg Problems

[Jamin]

Hello all,

After downloading the most recent version of fixed_pkg_c and
encountering many problems with synthesis, I started reading forum
posts and learned that the additions16 package was stable for '+' '-'
and '*' for many

Synthesis failed both using ISE 8.2 and also with ISE7.1, using XST for
synthesis. I tried synthesizing the following code with chipscope
implementation at the end of this post. I believe this test code is
okay, as I've followed examples done by other, any ideas or suggestions
to what may be wrong?

Thanks,
Jamin



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity test_fixed is

port (
in1, in2 : in std_logic_vector(9 downto 0); -- inputs
clk : in STD_LOGIC;
starter : out STD_LOGIC;
out1 : out std_logic_vector(10 downto 0)); -- output:

end entity test_fixed;

architecture description of test_fixed is

-------------
--COMPONENTS*
-------------
component vio
port
(
control : in std_logic_vector(35 downto 0);
async_out : out std_logic_vector(20 downto 0)
);
end component;

component icon
port
(
control0 : out std_logic_vector(35 downto 0);
control1 : out std_logic_vector(35 downto 0)
);
end component;

component ila
port
(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(10 downto 0);
trig0 : in std_logic_vector(0 downto 0)
);
end component;


----------
--SIGNALS*
----------
signal c : sfixed(5 downto -5);
signal resized_c : std_logic_vector(10 downto 0);

--ICON, ILA, VIO signals*
signal clk1 : std_logic;
signal trig0, temp_start : std_logic_vector(0 downto 0);
signal control_0,control_1 : std_logic_vector(35 downto 0);
signal async_out : std_logic_vector(20 downto 0);

begin -- architecture description

starter <= async_out(0);
temp_start(0) <= async_out(0);

process(clk,temp_start)
variable a,b : sfixed(4 downto -5);
begin
if temp_start(0) = '1' then
if (clk'Event and clk='1')then

a(4 downto -5) := to_sfixed(async_out(20 downto 11),4,-5);
b(4 downto -5) := to_sfixed(async_out(20 downto 11),4,-5);

c <= a + b;
end if;
else
c <= (others => '0');
a := (others => '0');
b := (others => '0');
end if;
end process;

out1 <= to_slv(c);
resized_c <= to_slv(c);

-- analyzer stuff
clk1 <= clk;

--------------
--virtual IO*
--------------
i_vio : vio
port map
(
control => control_0,
async_out => async_out
);

----------------------------
--integrated logic analyzer*
----------------------------
i_ila : ila
port map
(
control => control_1,
clk => clk1,
data => resized_c,
trig0 => temp_start
);

------------------------
--integrated controller*
------------------------
i_icon : icon
port map
(
control0 => control_0,
control1 => control_1
);

end architecture description;

 

[Mike Treseler]

Hello all,

After downloading the most recent version of fixed_pkg_c and
encountering many problems with synthesis, I started reading forum
posts and learned that the additions16 package was stable for '+' '-'

Consider posting a simple, component-free example
with the exact error messages
from simulation and synthesis,
and a link to the package under test.

-- Mike Treseler

 

[Jamin]

Hi Mike,
The package tested :
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/additions_16.tar.Z


The error produced by ISE8.2:

FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.16 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com


The error produced by ISE7.1:

ERROR:Xst:1548 - "E:/Users/Jamin/test_fixed/test_fixed.vhdl" line 17:
Negative range in type of signal <c> is not supported.
-->


The following code was used for synthesis. Thanks.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity test_fixed is
Port (clk : in std_logic;
in1, in2 : in std_logic_vector(9 downto 0);
out1 : out std_logic_vector(10 downto 0));
end test_fixed;

architecture description of test_fixed is

signal temp_out : std_logic_vector(10 downto 0);
signal c : sfixed(5 downto -5);

begin
process(clk, temp_start)
variable a,b : sfixed(4 downto -5);
begin
if temp_start(0) = '1' then
if(clk'Event and clk = '1') then
a(4 downto -5) := to_sfixed(in1,4,-5);
b(4 downto -5) := to_sfixed(in2,4,-5);
c <= a + b;
end if;
else
c <= (others => '0');
a := (others => '0');
b := (others => '0');
end if;
end process;

temp_out <= to_slv(c);
out1 <= temp_out;
end description;

 

[Jamin]

Hi Mike,
The package tested :
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/additions_16.tar.Z

The error produced by ISE8.2:


FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.16 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. To resolve this error, please

consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com


The error produced by ISE7.1:


ERROR:Xst:1548 - "E:/Users/Jamin/test_fixed/test_fixed.vhdl" line 17:
Negative range in type of signal <c> is not supported.
-->


The following code was used for synthesis. Thanks.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity test_fixed is
Port (clk : in std_logic;
in1, in2 : in std_logic_vector(9 downto 0);
out1 : out std_logic_vector(10 downto 0));
end test_fixed;

architecture description of test_fixed is

signal temp_out : std_logic_vector(10 downto 0);
signal c : sfixed(5 downto -5);

begin
process(clk)
variable a,b : sfixed(4 downto -5);
begin
if(clk'Event and clk = '1') then
a(4 downto -5) := to_sfixed(in1,4,-5);
b(4 downto -5) := to_sfixed(in2,4,-5);
c <= a + b;
else
c <= (others => '0');
a := (others => '0');
b := (others => '0');
end if;
end process;

temp_out <= to_slv(c);
out1 <= temp_out;
end description;

 

[Jamin]

Hi Mike,
The package tested :
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/additions_16.tar.Z


The error produced by ISE8.2:

Analyzing Entity <test_fixed> in library <work> (Architecture
<description>).
ERROR:Xst:827 - "C:/users/jamin/test_fixed/test_fixed.vhdl" line 20:
Signal c cannot be synthesized, bad synchronous description.
-->


The error produced by ISE7.1:

Analyzing Entity <test_fixed> (Architecture <description>).
ERROR:Xst:1548 - "E:/Users/Jamin/test_fixed/test_fixed.vhdl" line 17:
Negative range in type of signal <c> is not supported.
-->


The two ISE versions are running on different machines, the following
code was used for synthesis using XST. Thanks.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity test_fixed is
Port (clk : in std_logic;
in1, in2 : in std_logic_vector(9 downto 0);
out1 : out std_logic_vector(10 downto 0));
end test_fixed;

architecture description of test_fixed is

signal temp_out : std_logic_vector(10 downto 0);
signal c : sfixed(5 downto -5);

begin
process(clk)
variable a,b : sfixed(4 downto -5);
begin
if(clk'Event and clk = '1') then
a(4 downto -5) := to_sfixed(in1,4,-5);
b(4 downto -5) := to_sfixed(in2,4,-5);
c <= a + b;
else
c <= (others => '0');
a := (others => '0');
b := (others => '0');
end if;
end process;

temp_out <= to_slv(c);
out1 <= temp_out;
end description;

 

[Jamin]

Hi Mike,
The package tested :
http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/additions_16.tar.Z

The error produced by ISE8.2:

FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.16 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. To resolve this error, please
consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com


The error produced by ISE7.1:

Analyzing Entity <test_fixed> (Architecture <description>).
ERROR:Xst:1548 - "E:/Users/Jamin/test_fixed/test_fixed.vhdl" line 17:
Negative range in type of signal <c> is not supported.
-->


The two ISE versions are running on different machines, the following
code was used for synthesis using XST. Thanks.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity test_fixed is
Port (clk : in std_logic;
in1, in2 : in std_logic_vector(9 downto 0);
out1 : out std_logic_vector(10 downto 0));
end test_fixed;

architecture description of test_fixed is

signal temp_out : std_logic_vector(10 downto 0);
signal c : sfixed(5 downto -5);

begin
process(clk)
variable a,b : sfixed(4 downto -5);
begin
if(clk'Event and clk = '1') then
a(4 downto -5) := to_sfixed(in1,4,-5);
b(4 downto -5) := to_sfixed(in2,4,-5);
c <= a + b;
else
c <= (others => '0');
a := (others => '0');
b := (others => '0');
end if;
end process;

temp_out <= to_slv(c);
out1 <= temp_out;
end description;

 

[Andy]

Your test bench describes a circuit that adds two numbers on every
rising edge of the clock, and then on every falling edge ( clk'event
and not (clk = '1') ?) resets them and their sum to zero. While of
dubious value, this would require a double data rate (DDR) circuit to
implement, which is not available except as IO, and only on some
xilinx devices. There are methods of implementing DDR circuits with
SDR flops, but I doubt that is what you really wanted. Was there
supposed to be a reset (async or sync)?

Andy

 

[Jamin]

I was looking around on the forum and I found this, I guess it is a
problem with XST. Are there anyways around this now?

David Bishop
View profile
More options Nov 20 2004, 7:05 pm
Newsgroups: comp.lang.vhdl
From: David Bishop <[email protected]>
Date: Sun, 21 Nov 2004 00:05:55 GMT
Local: Sat, Nov 20 2004 7:05 pm
Subject: Re: VHDL-200X-FT Packages and Xilinx XST Error
Reply to author | Forward | Print | Individual message | Show original
|
Report this message | Find messages by this author

When trying to synthesize even
the simplest circuit using Xilinx XST (from 6.3.02i) I get the
following error:

Analyzing Entity <fp32_test> (Architecture <simple>).
ERROR:Xst:1548 - C:/MYModels/simple_fp_test_synthesis/simple_test.vhd
line 14: Negative range in type of signal <A> is not supported.
-->

I already told Xilinx about this. XST can not deal with a negative
index in Synthesis.

On the other side of the coin, Synopsys (Presto compiler), Exemplar
(Leonardo Spectrum), Synplicity, Cadence buildgates, and Altera
synthesis can.

The Xilinx help page isn't very helpful other than saying that it is
correct (search for: Xilinx answer #18974)

This is typical. XST is a REALLY cheap synthesis tool. I sent this
one into them over a year ago and it still isn't fixed.

Note that to get the packages to work I had to change the FP related
ieee.fp* to work.fp*. BTW, all the FP packages pass the XST
compilation stage.

If you need more information please let me know. I'm pretty sure
someone has run into this before and I'm doing something silly

Thanks for the test. Like I said, unless we can get Xilinx off it's
duff XST is a lost cause with these packages.