In their dream world, we would all switch to SystemVerilog.
No kidding about the marketing effort - this is a no brainer.
If one can convince the VHDL market to switch to SV, at a
minimum they will have to upgrade to enhanced licenses and
this means good revenue. Going further if you can also
convince VHDL users from your competitor that your tool is
better and they will switch. Even thinking about this makes
my eyes see $$$$ and I am not a marketing person
As for delivery from Accellera VHDL TC, DAC of 2006 (July)
is the required delivery date. Accellera is a different
model of working than IEEE. We have until 1 month before DAC to
deliver a standard that is approved by the Accellera VHDL
TC to the Accellera board. The development process has been
to prioritize items and work them through the process of
adding them to the LRM. What is done and approved 1 month
before DAC gets delivered. So the delivery date is set in
stone - the number of new features is negotiable, however,
at this point it looks like we are on track to deliver
what was started by VHDL-200X-FT plus numerous additional
enhancements.
BTW, if you are doing fixed and floating point math, the
Accellera VHDL-2006 adds fixed and floating point
math packages to the language. This is something that
you will not find in SystemVerilog.
Going further, there is also a working plan to start
immediately on the next revision. This revision will
include enhanced verification features such as constrained
random, OO, coverage, interfaces, and a direct programming
interface (DPI). It is at this phase where we will have
the same verification features that SV has. If we can do
this and maintain the clean language design currently
enjoyed by VHDL, then I think we will have a clearly
superior solution.
There is another key difference in the Accellera developement
process that means you will see vendors implementing new
features sooner. In Accellera, proposals are ranked by the
user community. As a result, vendors know that these are
features their user community wants. This is much different
from having a benevolent expert develop a feature only to
learn it does not solve the problems users are having
and as a result, any investment made in implementing the
feature was wasted since the feature was unused.
Rather than judging Accellera by its current pro SystemVerilog
front door, hold your judgement for DAC this year. When
they approve the Accellera VHDL-2006, then you know
that they are truely a multi-language organization.
I have to say, I had concerns about the pro SystemVerilog
stance of Accellera. However, I am impressed both with
the development process and with the effort put forward
by the VHDL technical committee to get this revision done.
Personally I have been putting in around 10 hours per week
on this effort a good portion of this time in meetings,
and I have been skipping half of the meetings.
Best Regards,
Jim
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Jim Lewis
Director of Training mailto:
[email protected]
SynthWorks Design Inc.
http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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