vhdl 200x status?

Discussion in 'VHDL' started by tkvhdl@gmail.com, Apr 29, 2006.

  1. Guest

    Does anyone know the status of VHDL 200x?
    When it might be completed?
    Has SystemVerilog killed off interest or is it still on track?
     
    , Apr 29, 2006
    #1
    1. Advertising

  2. Jim Lewis Guest

    VHDL-200X work was taken over by Accellera and
    there will be an approved Accellera draft of VHDL
    at or just after DAC in July 2006. This work
    adopts the majority of the VHDL-200X-FT plus
    additional proposals put forward by the Accellera
    VHDL TC.

    To find out more, you can join the Accellera TC (either
    as a member or not) and get access to the current
    status. There are links to Accellera VHDL TC through
    http://www.eda.org/vasg

    This draft is the first in a series of revisions.
    Following this draft there are proposals for adding
    constrained random, oo, and interfaces as well as
    a DPI (direct programming interface).

    Best Regards,
    Jim Lewis
    IEEE VASG Chair


    > Does anyone know the status of VHDL 200x?
    > When it might be completed?
    > Has SystemVerilog killed off interest or is it still on track?

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Apr 29, 2006
    #2
    1. Advertising

  3. Hans Guest

    > Has SystemVerilog killed off interest

    I believe this is happening, look at the amount of effort that EDA companies
    like Mentor is putting into SystemVerilog (and a bit in SystemC). The
    momentum of SystemVerilog is now so large that I wonder if companies can be
    steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
    Accellera doesn't produce something in say the next 2 years than IMHO VHDL
    is dead which is a real shame since I prefer it over Verilog.

    Hans
    www.ht-lab.com

    "" <> wrote in message
    news:...
    > Does anyone know the status of VHDL 200x?
    > When it might be completed?
    > Has SystemVerilog killed off interest or is it still on track?
    >
     
    Hans, Apr 29, 2006
    #3
  4. Phil Tomson Guest

    In article <FtF4g.1342$>,
    Hans <> wrote:
    >> Has SystemVerilog killed off interest

    >
    >I believe this is happening, look at the amount of effort that EDA companies
    >like Mentor is putting into SystemVerilog (and a bit in SystemC). The
    >momentum of SystemVerilog is now so large that I wonder if companies can be
    >steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
    >Accellera doesn't produce something in say the next 2 years than IMHO VHDL
    >is dead which is a real shame since I prefer it over Verilog.
    >


    You're probably right. What exactly is Accellera's incentive to produce
    a VHDL200x spec?
    From their website:
    "Accellera was formed in 2000 through the unification of Open Verilog
    International and VHDL International to focus on identifying new
    standards, development of standards and formats, and to foster the
    adoption of new methodologies."

    There's a SystemVerilog logo on their home page but I don't see anything
    about VHDL200x. They even let you download the SystemVerilog3.1a LRM -
    that's nice.

    Are (were) there many language syntax changes proposed for VHDL200x? Or
    was it mostly new packages? It seems like if it's the latter that the
    community might be able to drive this (more like what happens in the open
    source world). It's too bad that this all seems to be held hostage by a
    single company... at least that's how it seems, any other takes on this?

    Phil
     
    Phil Tomson, Apr 29, 2006
    #4
  5. Jim Lewis Guest

    In their dream world, we would all switch to SystemVerilog.
    No kidding about the marketing effort - this is a no brainer.
    If one can convince the VHDL market to switch to SV, at a
    minimum they will have to upgrade to enhanced licenses and
    this means good revenue. Going further if you can also
    convince VHDL users from your competitor that your tool is
    better and they will switch. Even thinking about this makes
    my eyes see $$$$ and I am not a marketing person :)

    As for delivery from Accellera VHDL TC, DAC of 2006 (July)
    is the required delivery date. Accellera is a different
    model of working than IEEE. We have until 1 month before DAC to
    deliver a standard that is approved by the Accellera VHDL
    TC to the Accellera board. The development process has been
    to prioritize items and work them through the process of
    adding them to the LRM. What is done and approved 1 month
    before DAC gets delivered. So the delivery date is set in
    stone - the number of new features is negotiable, however,
    at this point it looks like we are on track to deliver
    what was started by VHDL-200X-FT plus numerous additional
    enhancements.

    BTW, if you are doing fixed and floating point math, the
    Accellera VHDL-2006 adds fixed and floating point
    math packages to the language. This is something that
    you will not find in SystemVerilog.


    Going further, there is also a working plan to start
    immediately on the next revision. This revision will
    include enhanced verification features such as constrained
    random, OO, coverage, interfaces, and a direct programming
    interface (DPI). It is at this phase where we will have
    the same verification features that SV has. If we can do
    this and maintain the clean language design currently
    enjoyed by VHDL, then I think we will have a clearly
    superior solution.


    There is another key difference in the Accellera developement
    process that means you will see vendors implementing new
    features sooner. In Accellera, proposals are ranked by the
    user community. As a result, vendors know that these are
    features their user community wants. This is much different
    from having a benevolent expert develop a feature only to
    learn it does not solve the problems users are having
    and as a result, any investment made in implementing the
    feature was wasted since the feature was unused.

    Rather than judging Accellera by its current pro SystemVerilog
    front door, hold your judgement for DAC this year. When
    they approve the Accellera VHDL-2006, then you know
    that they are truely a multi-language organization.

    I have to say, I had concerns about the pro SystemVerilog
    stance of Accellera. However, I am impressed both with
    the development process and with the effort put forward
    by the VHDL technical committee to get this revision done.
    Personally I have been putting in around 10 hours per week
    on this effort a good portion of this time in meetings,
    and I have been skipping half of the meetings.

    Best Regards,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~







    >>Has SystemVerilog killed off interest

    >
    >
    > I believe this is happening, look at the amount of effort that EDA companies
    > like Mentor is putting into SystemVerilog (and a bit in SystemC). The
    > momentum of SystemVerilog is now so large that I wonder if companies can be
    > steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
    > Accellera doesn't produce something in say the next 2 years than IMHO VHDL
    > is dead which is a real shame since I prefer it over Verilog.
    >
    > Hans
    > www.ht-lab.com
    >
    > "" <> wrote in message
    > news:...
    >
    >>Does anyone know the status of VHDL 200x?
    >>When it might be completed?
    >>Has SystemVerilog killed off interest or is it still on track?
    >>

    >
    >
     
    Jim Lewis, Apr 30, 2006
    #5
  6. Jim Lewis Guest

    Phil,
    Before you make a judgement like this, I would encourage
    you to open the door and take a look inside and see what
    the Accellera VHDL TC is doing. In fact, since you did
    make an uninformed comment, you owe it to those of us
    who have been putting a great deal of "sweat" equity into
    this project.

    You do not need to join Accellera to join the Accellera
    VHDL TC. You only need to register with Accellera. Note
    that you do need to join Accellera however to have
    full voting rights.

    To register with Accellera, goto:
    http://www.accellera.org/activities/vhdl/

    On the line that states the following, press "click here"
    "If you are not an Accellera member and would like to
    join this group, _click here_ to contact us."

    In the comments field say:
    I would like to sign up for the Accellera VHDL TC


    Note that there are also other groups that under the VHDL TC that you
    may wish to join (requirements group, extensions group, review group,
    and LRM group).

    Send the form to: Lynn Horobin, Administration

    ---------------------------

    Once you have joined the Accellera VHDL TC, go to the following
    page and login:
    http://www.accellera.org/apps/org/workgroup/vhdl/documents.php


    To find out the current status of the effort, download the
    document: Requirements Status
    The latest one I looked at resolves to: RequirementsStatus_25Apr2006.xls
    If you look at the statistics in this file, there are 123 approved
    enhancements for this revision and 110 of them have approved
    LRM edits.

    Keep in mind, the main reason we miss requirements in language
    design is because either people fail to submit them or people
    who are interested in them fail to participate.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    > In article <FtF4g.1342$>,
    > Hans <> wrote:
    >
    >>>Has SystemVerilog killed off interest

    >>
    >>I believe this is happening, look at the amount of effort that EDA companies
    >>like Mentor is putting into SystemVerilog (and a bit in SystemC). The
    >>momentum of SystemVerilog is now so large that I wonder if companies can be
    >>steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
    >>Accellera doesn't produce something in say the next 2 years than IMHO VHDL
    >>is dead which is a real shame since I prefer it over Verilog.
    >>

    >
    >
    > You're probably right. What exactly is Accellera's incentive to produce
    > a VHDL200x spec?
    > From their website:
    > "Accellera was formed in 2000 through the unification of Open Verilog
    > International and VHDL International to focus on identifying new
    > standards, development of standards and formats, and to foster the
    > adoption of new methodologies."
    >
    > There's a SystemVerilog logo on their home page but I don't see anything
    > about VHDL200x. They even let you download the SystemVerilog3.1a LRM -
    > that's nice.
    >
    > Are (were) there many language syntax changes proposed for VHDL200x? Or
    > was it mostly new packages? It seems like if it's the latter that the
    > community might be able to drive this (more like what happens in the open
    > source world). It's too bad that this all seems to be held hostage by a
    > single company... at least that's how it seems, any other takes on this?
    >
    > Phil
     
    Jim Lewis, Apr 30, 2006
    #6
  7. Phil Tomson Guest

    In article <>,
    Jim Lewis <> wrote:
    >In their dream world, we would all switch to SystemVerilog.
    >No kidding about the marketing effort - this is a no brainer.
    >If one can convince the VHDL market to switch to SV, at a
    >minimum they will have to upgrade to enhanced licenses and
    >this means good revenue. Going further if you can also
    >convince VHDL users from your competitor that your tool is
    >better and they will switch. Even thinking about this makes
    >my eyes see $$$$ and I am not a marketing person :)
    >


    This is partly why I asked the question about incentives.
    What is Accellera's business model? Apparently they get revenue from dues
    paid by member companies (EDA companies). Are there other revenue
    streams?

    >
    >BTW, if you are doing fixed and floating point math, the
    >Accellera VHDL-2006 adds fixed and floating point
    >math packages to the language. This is something that
    >you will not find in SystemVerilog.


    Lots of us are eagerly awaiting this. However, even now the proposed
    fixed point packages are available and have been for a couple of years,
    right? Mostly they work great, however they have not worked with the
    Xilinx ISE/xst tools because they do not support negative indices (perhaps
    this has changed with ISE 8.1; I have not tried it).

    >
    >
    >Going further, there is also a working plan to start
    >immediately on the next revision. This revision will
    >include enhanced verification features such as constrained
    >random, OO, coverage, interfaces, and a direct programming
    >interface (DPI). It is at this phase where we will have
    >the same verification features that SV has. If we can do
    >this and maintain the clean language design currently
    >enjoyed by VHDL, then I think we will have a clearly
    >superior solution.


    Lots of great stuff there to be sure.

    >
    >
    >There is another key difference in the Accellera developement
    >process that means you will see vendors implementing new
    >features sooner. In Accellera, proposals are ranked by the
    >user community. As a result, vendors know that these are
    >features their user community wants. This is much different
    >from having a benevolent expert develop a feature only to
    >learn it does not solve the problems users are having
    >and as a result, any investment made in implementing the
    >feature was wasted since the feature was unused.
    >
    >Rather than judging Accellera by its current pro SystemVerilog
    >front door, hold your judgement for DAC this year. When
    >they approve the Accellera VHDL-2006, then you know
    >that they are truely a multi-language organization.
    >
    >I have to say, I had concerns about the pro SystemVerilog
    >stance of Accellera. However, I am impressed both with
    >the development process and with the effort put forward
    >by the VHDL technical committee to get this revision done.
    >Personally I have been putting in around 10 hours per week
    >on this effort a good portion of this time in meetings,
    >and I have been skipping half of the meetings.
    >


    Thanks for all the hard work.



    Phil
     
    Phil Tomson, May 1, 2006
    #7
  8. Phil Tomson Guest

    In article <>,
    Jim Lewis <> wrote:
    >Phil,
    >Before you make a judgement like this, I would encourage
    >you to open the door and take a look inside and see what
    >the Accellera VHDL TC is doing. In fact, since you did
    >make an uninformed comment, you owe it to those of us
    >who have been putting a great deal of "sweat" equity into
    >this project.


    Sorry, didn't mean to seem to call anyone's hard work into question.
    I thought that my comments were pretty tame, actually: basically just
    asked the question "what's in it for Accellera?". Even
    in your next reply after this one you mentioned that you yourself were
    wary about Accellera's seeming focus on SystemVerilog. A quick glance at
    their web page and it's pretty easy to come up with the impression that
    they're working on System Verilog. Sure if you dig deeper you can find
    that there is a VHDL TC. Maybe they could also have something like "We're
    the company working on the VHDL 200x spec - coming soon!" or some such. I
    think a lot of people are probably still under the impression that the
    IEEE was working on the VHDL 200x spec.

    I think part of what makes people wonder is that it's kind of hard to
    figure out what kind of 'animal' Accellera is. Is it an EDA company
    (apparently not, they don't seem to make any tools of their own). Is it a
    standardization committee? (well, it's apparently
    a for-profit company). What exactly is Accellera and where does their
    revenue come from? (seems to come from membership dues paid by EDA
    companies). Now, perhaps Accellera's VHDL 200x efforts are preferrable to
    the way that these sorts of things used to be done (in IEEE
    standardization committees). We'll find out.


    >
    >You do not need to join Accellera to join the Accellera
    >VHDL TC. You only need to register with Accellera. Note
    >that you do need to join Accellera however to have
    >full voting rights.
    >


    From the Accellera blurb on membership:
    "Annual corporate membership dues are $15,000 per year, while Associate
    membership is $5,000 per year."
    So basically that limits voting influence to the big-boys. Most of us see
    that as saying: "this is an exclusive club and we don't want any riff-raff
    hanging around". Those of us from more of an open-source orientation have
    a hard time relating. Even small commercial startup EDA companies might
    not have the resources to become members.


    >To register with Accellera, goto:
    > http://www.accellera.org/activities/vhdl/
    >
    >On the line that states the following, press "click here"
    > "If you are not an Accellera member and would like to
    > join this group, _click here_ to contact us."


    But if membership has it's priviledges, what exactly can one do if one is
    not a member but has 'joined the group'?

    >
    >In the comments field say:
    >I would like to sign up for the Accellera VHDL TC
    >
    >
    >Note that there are also other groups that under the VHDL TC that you
    >may wish to join (requirements group, extensions group, review group,
    >and LRM group).
    >
    >Send the form to: Lynn Horobin, Administration
    >
    >---------------------------
    >
    >Once you have joined the Accellera VHDL TC, go to the following
    >page and login:
    >http://www.accellera.org/apps/org/workgroup/vhdl/documents.php
    >
    >
    >To find out the current status of the effort, download the
    >document: Requirements Status
    >The latest one I looked at resolves to: RequirementsStatus_25Apr2006.xls
    >If you look at the statistics in this file, there are 123 approved
    >enhancements for this revision and 110 of them have approved
    >LRM edits.
    >
    >Keep in mind, the main reason we miss requirements in language
    >design is because either people fail to submit them or people
    >who are interested in them fail to participate.
    >


    To what extent can non-members participate? this is an honest question, I
    am not trying to be belligerant. We've all got very limited time and for
    those of us who are used to participating in open-source efforts a cursory
    glance at the Accellera website reveals a world alien to us so we're more
    likely to move along to put our efforts into an open-source project (like
    open cores or Icarus Verilog or ghdl...)

    Phil
     
    Phil Tomson, May 1, 2006
    #8
  9. Hans Guest

    Hi Jim,

    I know you are actively promoting VHDL-200X (I have seen your MAPLD
    presentation :). However, you seem to be the only person doing it, I see
    hardly any papers, magazine articles, newsgroup postings etc on VHDL-200X
    standard. On the 2002 standard, how many VHDL engineers can list the
    difference with the 1993 standard? Why do you think that is?

    I haven't checked the documents on the Accellera website but from your
    presentation it seems that the VHDL-200X standard will be just a clean-up of
    the language (PSL being the exception) and something which should have been
    added to the 1076-2002 standard? All the goodies that (verification)
    engineers need like Constrained Random, OO (so I have been told:) and a
    simpler C interface will be looked at after DAC06? are we looking at another
    5 years?

    Is Aart de Geus in charge of the committee? :)

    Hans
    www.ht-lab.com

    "Jim Lewis" <> wrote in message
    news:...
    > In their dream world, we would all switch to SystemVerilog.
    > No kidding about the marketing effort - this is a no brainer.
    > If one can convince the VHDL market to switch to SV, at a
    > minimum they will have to upgrade to enhanced licenses and
    > this means good revenue. Going further if you can also
    > convince VHDL users from your competitor that your tool is
    > better and they will switch. Even thinking about this makes
    > my eyes see $$$$ and I am not a marketing person :)
    >
    > As for delivery from Accellera VHDL TC, DAC of 2006 (July)
    > is the required delivery date. Accellera is a different
    > model of working than IEEE. We have until 1 month before DAC to
    > deliver a standard that is approved by the Accellera VHDL
    > TC to the Accellera board. The development process has been
    > to prioritize items and work them through the process of
    > adding them to the LRM. What is done and approved 1 month
    > before DAC gets delivered. So the delivery date is set in
    > stone - the number of new features is negotiable, however,
    > at this point it looks like we are on track to deliver
    > what was started by VHDL-200X-FT plus numerous additional
    > enhancements.
    >
    > BTW, if you are doing fixed and floating point math, the
    > Accellera VHDL-2006 adds fixed and floating point
    > math packages to the language. This is something that
    > you will not find in SystemVerilog.
    >
    >
    > Going further, there is also a working plan to start
    > immediately on the next revision. This revision will
    > include enhanced verification features such as constrained
    > random, OO, coverage, interfaces, and a direct programming
    > interface (DPI). It is at this phase where we will have
    > the same verification features that SV has. If we can do
    > this and maintain the clean language design currently
    > enjoyed by VHDL, then I think we will have a clearly
    > superior solution.
    >
    >
    > There is another key difference in the Accellera developement
    > process that means you will see vendors implementing new
    > features sooner. In Accellera, proposals are ranked by the
    > user community. As a result, vendors know that these are
    > features their user community wants. This is much different
    > from having a benevolent expert develop a feature only to
    > learn it does not solve the problems users are having
    > and as a result, any investment made in implementing the
    > feature was wasted since the feature was unused.
    >
    > Rather than judging Accellera by its current pro SystemVerilog
    > front door, hold your judgement for DAC this year. When
    > they approve the Accellera VHDL-2006, then you know
    > that they are truely a multi-language organization.
    >
    > I have to say, I had concerns about the pro SystemVerilog
    > stance of Accellera. However, I am impressed both with
    > the development process and with the effort put forward
    > by the VHDL technical committee to get this revision done.
    > Personally I have been putting in around 10 hours per week
    > on this effort a good portion of this time in meetings,
    > and I have been skipping half of the meetings.
    >
    > Best Regards,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    >
    >
    >
    >
    >
    >
    >
    >>>Has SystemVerilog killed off interest

    >>
    >>
    >> I believe this is happening, look at the amount of effort that EDA
    >> companies
    >> like Mentor is putting into SystemVerilog (and a bit in SystemC). The
    >> momentum of SystemVerilog is now so large that I wonder if companies can
    >> be
    >> steered toward SystemVHDL/HyperVHDL whenever it becomes available. If
    >> Accellera doesn't produce something in say the next 2 years than IMHO
    >> VHDL
    >> is dead which is a real shame since I prefer it over Verilog.
    >>
    >> Hans
    >> www.ht-lab.com
    >>
    >> "" <> wrote in message
    >> news:...
    >>
    >>>Does anyone know the status of VHDL 200x?
    >>>When it might be completed?
    >>>Has SystemVerilog killed off interest or is it still on track?
    >>>

    >>
     
    Hans, May 1, 2006
    #9
  10. Phil Tomson wrote:

    > A quick glance at
    > their web page and it's pretty easy to come up with the impression that
    > they're working on System Verilog.


    My take is that verilog is in much greater
    need of an update than is vhdl. If you look
    at a list of the new features, there is little
    that is not already covered in vhdl93.
    It is easier to hype and sell products
    with large improvements than sell upgrades.

    > What exactly is Accellera and where does their
    > revenue come from? (seems to come from membership dues paid by EDA
    > companies).


    It is an association of companies that
    make money on eda software by selling,
    promoting, or training.

    Now, perhaps Accellera's VHDL 200x efforts are preferrable to
    > the way that these sorts of things used to be done (in IEEE
    > standardization committees). We'll find out.


    The IEEE process was glacial.

    > So basically that limits voting influence to the big-boys.


    Yes, and like it or not, the big boys in the U.S. use verilog.

    -- Mike Treseler
     
    Mike Treseler, May 1, 2006
    #10
  11. Jim Lewis Guest

    Hans,
    > I know you are actively promoting VHDL-200X (I have seen your MAPLD
    > presentation :). However, you seem to be the only person doing it, I see
    > hardly any papers, magazine articles, newsgroup postings etc on VHDL-200X
    > standard. On the 2002 standard, how many VHDL engineers can list the
    > difference with the 1993 standard? Why do you think that is?


    I have done many of the papers because I am at the conferences
    anyway. Besides I like doing presentations and many engineers
    don't. There are lots of people behind the scenes doing great
    work - I just like getting up and yacking about it.

    Very little changed in 2002 (3 items?). On the other hand,
    in 2004, there are 123 approved enhancements and 110 of those
    are done and in the LRM.

    > I haven't checked the documents on the Accellera website but from your
    > presentation it seems that the VHDL-200X standard will be just a clean-up of
    > the language (PSL being the exception) and something which should have been
    > added to the 1076-2002 standard?


    You are right, very little was added to 1076-2002. It is
    unfortunate. This is the direct result of the standard
    revisions being left to "someone else". Join and help with
    the standard. There is lots to do. See my previous post
    for details.

    > All the goodies that (verification)
    > engineers need like Constrained Random, OO (so I have been told:) and a
    > simpler C interface will be looked at after DAC06? are we looking at another
    > 5 years?


    These are the next set of features to be worked on. I would
    be surprised if the committee does not have Constrained
    Random, OO, and Interfaces done by DAC 07 if not sooner.

    They are a high priority. Unfortunately since they did not
    have sufficient prior work, it was not possible to get them
    done for this revision. This was a tactical mistake of the
    VHDL-200X effort. The focus there was "Fast Track" which
    unfortunately dragged due to lack of a funding model.


    > Is Aart de Geus in charge of the committee? :)

    Ouch. That is not very nice.

    Lance Thompson of IBM is the VHDL TC chair and he has
    been doing a great job leading the group.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 1, 2006
    #11
  12. Jim Lewis Guest

    Mike,
    >> the way that these sorts of things used to be done (in IEEE
    >> standardization committees). We'll find out.

    >
    >
    > The IEEE process was glacial.


    Under just IEEE, there is no funding model. Every group
    has to invent their own. As a result, it is very difficult
    to get VHDL LRM work done as it takes lots of effort - more
    than one can do on a voluntary basis.

    Ironically IEEE does not fund standards working groups.
    IEEE does not even fund the IEEE-SA (standards association).
    This might surprise you. What shocked me is that it even
    surprises some IEEE board members when they learn this.
    The unfortunate part of the situation is that the IEEE board
    are volunteers and they only have a term of 1 year. As soon
    as they get oriented to the system, they are out the door.


    >> So basically that limits voting influence to the big-boys.


    What I have found is that most of the decision making has
    been at the subgroup level. In the subgroup, everyone has
    a say and the decision is by consensus. Only if consensus
    cannot be reached is a member based TC vote conducted.
    This does not happen often.

    Given that we rarely go to a member based TC vote, the
    reality of the situation is that those who are participating
    have a great deal of influence. As a group we all ranked
    the requests. Then someone worked on the proposal. In
    writing proposals you have a direct impact on what gets
    considered and what gets done. If there is no one
    interested in a request, then it does not get worked on.

    The biggest way you don't get a say is by not participating.

    > Yes, and like it or not, the big boys in the U.S. use verilog.


    Ammend that to the "commercial" ASIC big boys do Verilog.
    Further refining that, how many of them are still doing
    the majority of their engineering in the US?

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 1, 2006
    #12
  13. Jim Lewis Guest

    Phil,
    > Sorry, didn't mean to seem to call anyone's hard work into question.
    > I thought that my comments were pretty tame, actually: basically just
    > asked the question "what's in it for Accellera?". ...
    > ... what kind of 'animal' is Accellera?


    Accellera is a standards incubation organization. I suspect
    they are a non-profit, but I don't know for sure.

    Accellera is directed by a board composed of its member
    companies. To successfully move VHDL to Accellera, we
    had to convince enough user companies to join the Accellera
    board. With that we were able to orgainze a VHDL technical
    committee and request funding - which was granted.



    >>You do not need to join Accellera to join the Accellera
    >>VHDL TC. You only need to register with Accellera. Note
    >>that you do need to join Accellera however to have
    >>full voting rights.
    >>

    >
    > From the Accellera blurb on membership:
    > "Annual corporate membership dues are $15,000 per year, while Associate
    > membership is $5,000 per year."
    > So basically that limits voting influence to the big-boys. Most of us see
    > that as saying: "this is an exclusive club and we don't want any riff-raff
    > hanging around". ...
    > ... Even small commercial startup EDA companies might
    > not have the resources to become members.


    What I have found is that most of the decision making has
    been at the subgroup level. In the subgroup, everyone has
    a say and the decision is by consensus. Only if consensus
    cannot be reached is a member based TC vote conducted.
    This does not happen often.

    Given that we rarely go to a member based TC vote, the
    reality of the situation is that those who are participating
    have a great deal of influence. As a group we all ranked
    the requests. Then someone worked on the proposal. In
    writing proposals you have a direct impact on what gets
    considered and what gets done. If there is no one
    interested in a request, then it does not get worked on.

    The biggest way you don't get a say is by not participating.

    If you contribute, most industry standards groups will
    welcome your participation. After all from a business
    standpoint, who would turn away free labor?

    > Those of us from more of an open-source orientation
    > have a hard time relating.

    Open source is not totally laisse-faire is it?
    Someone or some limited group is approving things right?


    > To what extent can non-members participate? this is an honest question, I
    > am not trying to be belligerant. We've all got very limited time and for
    > those of us who are used to participating in open-source efforts a cursory
    > glance at the Accellera website reveals a world alien to us so we're more
    > likely to move along to put our efforts into an open-source project (like
    > open cores or Icarus Verilog or ghdl...)


    I am not sure how open source projects work, but I suspect it
    is more like them than not.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 1, 2006
    #13
  14. Jim Lewis Guest

    Phil,
    >>BTW, if you are doing fixed and floating point math, the
    >>Accellera VHDL-2006 adds fixed and floating point
    >>math packages to the language. This is something that
    >>you will not find in SystemVerilog.

    >
    >
    > Lots of us are eagerly awaiting this. However, even now the proposed
    > fixed point packages are available and have been for a couple of years,
    > right? Mostly they work great, however they have not worked with the
    > Xilinx ISE/xst tools because they do not support negative indices (perhaps
    > this has changed with ISE 8.1; I have not tried it).


    Not sure where Xilinx is at this point, but I have heard
    that getting these packages working is a priority for them.
    I also have not upgraded to ISE 8.1 yet so I don't know if
    it is fixed or not.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 1, 2006
    #14
  15. Guest

    Thanks for the updates on VHDL progress. Great to see something will
    happen at DAC.
    Seems like Mentor and Cadence supported SystemVerilog way before the
    final specification.
    Does anyone have an inside scoop on their (potential) support for VHDL
    200x?
     
    , May 1, 2006
    #15
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