VHDL aggregates assignment

Discussion in 'VHDL' started by bkuschak@gmail.com, Sep 12, 2005.

  1. Guest

    Is it possible to use aggregates to perform the inverse of this
    concatenation operation:

    signal d : std_logic_vector(11 downto 0);
    signal a1, b1, c1 : std_logic_vector(3 downto 0);
    d <= a1 & b1 & c1;

    With something like this:

    signal a2, b2, c2 : std_logic_vector(3 downto 0);
    (a2, b2, c2) <= d;

    This syntax doesn't work, as the signals are vectors, not std_logic. I
    probably just don't have the syntax right. I'd like to use this method
    as it is less error prone than the following, especially if lengths are
    changed later:

    a2 <= d(11 downto 8);
    b2 <= d(7 downto 4);
    c2 <= d(3 downto 0);

    Thanks,
    Brian
     
    , Sep 12, 2005
    #1
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  2. wrote:
    > Is it possible to use aggregates to perform the inverse of this
    > concatenation operation

    ....
    > With something like this:
    >
    > signal a2, b2, c2 : std_logic_vector(3 downto 0);
    > (a2, b2, c2) <= d;


    Yes, but it's probably more trouble than you expect.
    You have to declare some types and subtypes.
    See below:
    (aa,bb,cc) := twelve_bit;

    -- Mike Treseler

    ___________________________________________________________

    library ieee;
    use ieee.std_logic_1164.all;
    -- use ieee.numeric_std.all;
    -- Mon Sep 12 15:27:54 2005 Mike Treseler
    entity aggregate is
    end entity aggregate;

    architecture play of aggregate is
    begin
    what : process is
    variable a, b, c, d : std_ulogic;
    subtype u3_t is std_logic_vector(2 downto 0);
    subtype u4_t is std_logic_vector(3 downto 0);
    type u4x3_t is array (0 to 2) of u4_t;
    variable twelve_bit : u4x3_t := ("0000","1111","1010");
    variable four_bit, aa,bb,cc : u4_t;
    variable three_bit : u3_t;
    begin -- process what
    -- assign 4 bits to aggregate
    -- vector type qualification required on right.
    (a, b, c, d) := std_logic_vector'("0011");
    -- assign four bit vector from aggregate
    four_bit := (a, b, c, d);
    assert four_bit = "0011" report "not 3";
    -- reverse 4 bit values using two aggregates
    -- vector type qualification required on right.
    (d, c, b, a) := std_logic_vector'(a, b, c, d);
    -- assign reversed values to vector
    four_bit := (a, b, c, d);
    assert four_bit = "1100" report "not 12";
    three_bit := (a, b, c);
    -- assign three small vectors from type u4x3_t
    (aa,bb,cc) := twelve_bit;
    assert cc = "1010" report "cc error";
    assert bb = "1111" report "bb error";
    assert aa = "0000" report "aa error";
    report("Expect no assertions above.");
    wait;
    end process what;
    end architecture play;
    -------------------------------------------------------------------------------
    --# vsim -c aggregate
    --# Loading /steptoe/usr1/modeltech/linux/../std.standard
    --# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
    --# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
    --# Loading play.aggregate(play)

    --VSIM 1> run 1
    --# ** Note: Expect no assertions above.
    --# Time: 0 ns Iteration: 0 Instance: /aggregate
    --VSIM 2>
     
    Mike Treseler, Sep 13, 2005
    #2
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  3. Guest

    Yeah, I figured it would require something like that.
    Thanks,
    Brian
     
    , Sep 16, 2005
    #3
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