VHDL and MATLAB

Discussion in 'VHDL' started by dimmutal, Feb 27, 2006.

  1. dimmutal

    dimmutal

    Joined:
    Feb 27, 2006
    Messages:
    1
    Hi there,

    I would like to know how to enter an input from Simulink to a VHDL model i have.
    I have made several simulations but the case here is that my input port of my entity is an array of std_logic_vector. I have used succesfully the Random Number Generator in Simulink as an input to a simple std_logic_vector input port, but i can't find a way to enter an input to an ARRAY of std_logic_vector. Any recommendations?
    dimmutal, Feb 27, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Emel
    Replies:
    0
    Views:
    3,621
  2. Emel
    Replies:
    0
    Views:
    869
  3. ronak283@gmail.com

    Matlab and VHDL

    ronak283@gmail.com, Dec 1, 2006, in forum: VHDL
    Replies:
    2
    Views:
    799
    Ralf Hildebrandt
    Dec 2, 2006
  4. siki
    Replies:
    0
    Views:
    936
  5. Luna Moon
    Replies:
    16
    Views:
    1,311
    Giovanni Gherdovich
    Aug 8, 2008
Loading...

Share This Page