VHDL and ports

Discussion in 'VHDL' started by Brad Smallridge, Oct 11, 2004.

  1. Just a reality check here for a beginner.

    I am under the impression, although I haven't actually seen it written, that
    all IO ports have to come up through the hierarchy of entities to be
    expressed at the top level. Is this true? Or can you have some IO ports
    handled by lower entities, such as setting a control level to 1 or 0, and
    not having the "hooks" go up to the high level?

    Brad Smallridge
    b r a d @ a i v i s i o n . c o m
    Brad Smallridge, Oct 11, 2004
    #1
    1. Advertising

  2. Brad Smallridge wrote:
    >
    > I am under the impression, although I haven't actually seen it written, that
    > all IO ports have to come up through the hierarchy of entities to be
    > expressed at the top level. Is this true?


    Yes. One reason to minimize the number of levels.

    http://groups.google.com/groups?q=my_entity top wiring isaac

    -- Mike Treseler
    Mike Treseler, Oct 12, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. David Jones

    Are generics and ports static names?

    David Jones, Feb 20, 2004, in forum: VHDL
    Replies:
    0
    Views:
    582
    David Jones
    Feb 20, 2004
  2. afd
    Replies:
    1
    Views:
    8,321
    Colin Paul Gloster
    Mar 23, 2007
  3. Replies:
    6
    Views:
    697
  4. mreister
    Replies:
    1
    Views:
    3,162
    mreister
    May 25, 2010
  5. Phil Tomson
    Replies:
    3
    Views:
    125
    Joel VanderWerf
    Aug 31, 2006
Loading...

Share This Page