VHDL and .txt

Discussion in 'VHDL' started by Ronny Hengst, Jun 24, 2003.

  1. Ronny Hengst

    Ronny Hengst Guest

    Hello

    I want read in a .txt-file with VHDL.
    For example

    a 0 1 ns
    b 1 1 ns
    c 0 1 ns
    d 0 1 ns
    sel 01 1 ns

    a,b,c,d are variables from type std_logic, sel from type std_logic_vector.
    Can somebody help me?

    Thanks
    Ronny Hengst, Jun 24, 2003
    #1
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  2. "Ronny Hengst" <> wrote:
    > I want read in a .txt-file with VHDL.

    [..]
    > a,b,c,d are variables from type std_logic, sel from type std_logic_vector.
    > Can somebody help me?


    Std_logic_textio is the library of your desire.

    bye Thomas
    Thomas Stanka, Jun 25, 2003
    #2
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  3. Hi

    BTW.
    It's not possible to read std_logic or std_logic_vector, so you better
    read characters and use a conversion function char2std_logic or
    char2std_logic_vector.
    You probably have to write your own conversion functions.

    You may also go with reading bit and bitvector instead of std_logic and
    std_logic_vector.

    HTH

    Ansgar

    --
    Attention please, reply address is invalid, please remove "_xxx_" ro reply


    "Ronny Hengst" <> schrieb im Newsbeitrag
    news:bdachs$qm5ks$...
    > Hello
    >
    > I want read in a .txt-file with VHDL.
    > For example
    >
    > a 0 1 ns
    > b 1 1 ns
    > c 0 1 ns
    > d 0 1 ns
    > sel 01 1 ns
    >
    > a,b,c,d are variables from type std_logic, sel from type std_logic_vector.
    > Can somebody help me?
    >
    > Thanks
    >
    >
    Ansgar Bambynek, Jun 25, 2003
    #3
  4. Ronny Hengst

    Amontec Team Guest

    Ansgar Bambynek wrote:
    > Hi
    >
    > BTW.
    > It's not possible to read std_logic or std_logic_vector, so you better
    > read characters and use a conversion function char2std_logic or
    > char2std_logic_vector.
    > You probably have to write your own conversion functions.
    >
    > You may also go with reading bit and bitvector instead of std_logic and
    > std_logic_vector.
    >
    > HTH
    >
    > Ansgar
    >
    > --
    > Attention please, reply address is invalid, please remove "_xxx_" ro reply
    >
    >
    > "Ronny Hengst" <> schrieb im Newsbeitrag
    > news:bdachs$qm5ks$...
    >
    >>Hello
    >>
    >>I want read in a .txt-file with VHDL.
    >>For example
    >>
    >>a 0 1 ns
    >>b 1 1 ns
    >>c 0 1 ns
    >>d 0 1 ns
    >>sel 01 1 ns
    >>
    >>a,b,c,d are variables from type std_logic, sel from type std_logic_vector.
    >>Can somebody help me?
    >>
    >>Thanks
    >>
    >>

    >
    >
    >


    What?

    The library IEEE.STD.textio.all supports STD_LOGIC_VECTOR
    STD_ULOGIC_VECTOR read !

    Look at

    procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC);
    procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH :=0);

    ....

    BUT I DON'T LIKE IEEE.STD.textio.all, BUT I USE STD.textio.all from STD
    and not from IEEE.

    Laurent
    Amontec Team
    www.amontec



    package STD_LOGIC_TEXTIO is
    --synopsys synthesis_off
    -- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR

    procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC; GOOD: out BOOLEAN);
    procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC
    procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);

    -- Read and Write procedures for STD_LOGIC_VECTOR
    procedure READ(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    procedure READ(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);

    --
    -- Read and Write procedures for Hex and Octal values.
    -- The values appear in the file as a series of characters
    -- between 0-F (Hex), or 0-7 (Octal) respectively.
    --

    -- Hex
    procedure HREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    procedure HREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    procedure HREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    procedure HREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);

    -- Octal
    procedure OREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    procedure OREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    procedure OREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    procedure OREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    BOOLEAN);
    procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    Amontec Team, Jun 25, 2003
    #4
  5. Hi

    I was referencing the std.textio package since I wasn't aware of the
    std_logic_textio package.
    This package doesn't have the feature of reading std_logic.

    So if you don't like the ieee version as you mentioned below and use
    std.textio.all
    you will not be able to read std_logic or std_logic_vector.

    If you have a look at the ieee.std_logic_textio they use a conversion
    function
    to read in a char and return a std_logic.

    BTW. the ieee.std_logic_textio was developed by Synopsys and I'm not
    sure if it is part of the standard. At least it cannot be found in the LRM.

    Neverthess this package is include (as source code and compiled) within
    MTI's vsim.

    Ansgar

    --
    Attention please, reply address is invalid, please remove "_xxx_" ro reply
    "Amontec Team" <> schrieb im
    Newsbeitrag news:...
    > Ansgar Bambynek wrote:
    > > Hi
    > >
    > > BTW.
    > > It's not possible to read std_logic or std_logic_vector, so you better
    > > read characters and use a conversion function char2std_logic or
    > > char2std_logic_vector.
    > > You probably have to write your own conversion functions.
    > >
    > > You may also go with reading bit and bitvector instead of std_logic and
    > > std_logic_vector.
    > >
    > > HTH
    > >
    > > Ansgar
    > >
    > > --
    > > Attention please, reply address is invalid, please remove "_xxx_" ro

    reply
    > >
    > >
    > > "Ronny Hengst" <> schrieb im Newsbeitrag
    > > news:bdachs$qm5ks$...
    > >
    > >>Hello
    > >>
    > >>I want read in a .txt-file with VHDL.
    > >>For example
    > >>
    > >>a 0 1 ns
    > >>b 1 1 ns
    > >>c 0 1 ns
    > >>d 0 1 ns
    > >>sel 01 1 ns
    > >>
    > >>a,b,c,d are variables from type std_logic, sel from type

    std_logic_vector.
    > >>Can somebody help me?
    > >>
    > >>Thanks
    > >>
    > >>

    > >
    > >
    > >

    >
    > What?
    >
    > The library IEEE.STD.textio.all supports STD_LOGIC_VECTOR
    > STD_ULOGIC_VECTOR read !
    >
    > Look at
    >
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC);
    > procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH :=0);
    >
    > ...
    >
    > BUT I DON'T LIKE IEEE.STD.textio.all, BUT I USE STD.textio.all from STD
    > and not from IEEE.
    >
    > Laurent
    > Amontec Team
    > www.amontec
    >
    >
    >
    > package STD_LOGIC_TEXTIO is
    > --synopsys synthesis_off
    > -- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
    >
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC; GOOD: out BOOLEAN);
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC
    > procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    >
    > -- Read and Write procedures for STD_LOGIC_VECTOR
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    > procedure READ(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    >
    > --
    > -- Read and Write procedures for Hex and Octal values.
    > -- The values appear in the file as a series of characters
    > -- between 0-F (Hex), or 0-7 (Octal) respectively.
    > --
    >
    > -- Hex
    > procedure HREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    > procedure HREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    > procedure HREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    > procedure HREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    >
    > -- Octal
    > procedure OREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR);
    > procedure OREAD(L:inout LINE; VALUE:eek:ut STD_ULOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    > procedure OREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR);
    > procedure OREAD(L:inout LINE; VALUE:eek:ut STD_LOGIC_VECTOR; GOOD: out
    > BOOLEAN);
    > procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
    > JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
    >
    Ansgar Bambynek, Jun 26, 2003
    #5
  6. Ronny Hengst

    Jim Lewis Guest

    Ronny,
    To read std_logic_vector, you can use the package
    ieee.std_logic_textio.all. Note this is not a standard
    package (yet), but it is freeware and seems to be
    distributed with most simulators. My recommendation would
    be to just use it.

    Alternately if you are not reading values other than 0
    and 1, you could read it in as bit or bit_vector and
    then convert it to std_logic/std_logic_vector.
    You can use the functions to_stdulogic/to_stdlogicvector
    or to_x01/to_x01 (a little more cryptic as to your intent).

    I think this answers the small question, but I would
    not recommend creating stimulus this way. I would recommend
    that you create most of your stimulus in VHDL code.
    One thing to think about is the interface actions (transactions)
    and write a procedure that can do the entire sequence with
    the input of a few data values.

    The kind of stimulus I put in a file is something like the
    values for entire ethernet packet (or several of them), but
    I avoid putting timing and control type features in the
    file.

    Cheers,
    Jim

    P.S. We have a three day class on putting together
    transaction-based testbenches. Details are at:
    http://www.synthworks.com/VhdlTest.htm

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    Ronny Hengst wrote:
    > Hello
    >
    > I want read in a .txt-file with VHDL.
    > For example
    >
    > a 0 1 ns
    > b 1 1 ns
    > c 0 1 ns
    > d 0 1 ns
    > sel 01 1 ns
    >
    > a,b,c,d are variables from type std_logic, sel from type std_logic_vector.
    > Can somebody help me?
    >
    > Thanks
    >
    >
    Jim Lewis, Jun 26, 2003
    #6
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