VHDL assign multiple concatenated signals

Discussion in 'VHDL' started by veevee1, Mar 7, 2007.

  1. veevee1

    veevee1

    Joined:
    Mar 7, 2007
    Messages:
    5
    Hello,

    Is there a way to assign to multiple concatenated signals without having to rip the bits and assign each signal individually? For example:

    byte0 : std_logic_vector(7 downto 0);
    byte1.....

    data_vector_32_bit : std_logic_vector(31 downto 0);


    Is it possible to assign:

    byte0 & byte1 & byte2 & byte3 <= data_vector_32_bit;


    The compiler didnt accept this kind of assignment but is there a technique to do it some other simple way (oneliner)?
     
    veevee1, Mar 7, 2007
    #1
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