[VHDL Beginner] About ressources used

Discussion in 'VHDL' started by Pascal Peyremorte, Jul 20, 2005.

  1. Hi,

    I am beginning in VHDL and FPGA world, and I want to understand a bit
    more about better code for a 4 bits adder :

    entity ADD4 is
    port(VAL1 : in std_logic_vector(3 downto 0);
    VAL2 : in std_logic_vector(3 downto 0);
    SOMME : out std_logic_vector(3 downto 0);
    RETENUE : out std_logic);
    end ADD4;
    Note : SOMME = French(SUM); RETENUE = French(CARRY) (.. Sorry !)

    I found this architecture in a tutorial :

    architecture ADD4_INT of ADD4 is
    signal INT_SOMME : std_logic_vector(4 downto 0);
    signal INT_VAL1 : std_logic_vector(4 downto 0);
    signal INT_VAL2 : std_logic_vector(4 downto 0);
    begin
    INT_VAL1 <= '0' & VAL1;
    INT_VAL2 <= '0' & VAL2;
    INT_SOMME <= INT_VAL1 + INT_VAL2;
    SOMME <= INT_SOMME(3 downto 0);
    RETENUE <= INT_SOMME(4);
    end ADD4_INT;

    and write that one :

    architecture ADD4_BOOL of ADD4 is
    signal C0, C1, C2 : std_logic;
    begin
    SOMME(0) <= VAL1(0) xor VAL2(0);
    C0 <= VAL1(0) and VAL2(0);

    SOMME(1) <= VAL1(1) xor VAL2(1) xor C0;
    C1 <= (VAL1(1) and VAL2(1)) or (C0 and (Val1(1) or Val2(1)));

    SOMME(2) <= VAL1(2) xor VAL2(2) xor C1;
    C2 <= (VAL1(2) and VAL2(2)) or (C1 and (Val1(2) or Val2(2)));

    SOMME(3) <= VAL1(3) xor VAL2(3) xor C2;
    RETENUE <= (VAL1(3) and VAL2(3)) or (C2 and (Val1(3) or Val2(3)));
    end ADD4_BOOL;

    It seems to me that the first one look like shorter but may allocate
    more resources because of the many 5 bits "SIGNAL"

    Am I right ?
    Have you any comment about the two architectures ?

    Thank you very much
    Pascal
    Pascal Peyremorte, Jul 20, 2005
    #1
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  2. On Wed, 20 Jul 2005 22:53:10 +0200, Pascal Peyremorte
    <> wrote:

    >I am beginning in VHDL and FPGA world, and I want to understand a bit
    >more about better code for a 4 bits adder :

    [...]
    >I found this architecture in a tutorial :
    >
    >architecture ADD4_INT of ADD4 is
    > signal INT_SOMME : std_logic_vector(4 downto 0);
    > signal INT_VAL1 : std_logic_vector(4 downto 0);
    > signal INT_VAL2 : std_logic_vector(4 downto 0);
    >begin
    > INT_VAL1 <= '0' & VAL1;
    > INT_VAL2 <= '0' & VAL2;
    > INT_SOMME <= INT_VAL1 + INT_VAL2;
    > SOMME <= INT_SOMME(3 downto 0);
    > RETENUE <= INT_SOMME(4);
    >end ADD4_INT;


    That will work if you include

    use IEEE.std_logic_unsigned.all;

    at the beginning of your code.
    However, I suggest you try to find out about the "numeric_std"
    package, which offers a better way to do arithmetic on
    vector signals.

    >architecture ADD4_BOOL of ADD4 is
    > signal C0, C1, C2 : std_logic;
    >begin
    > SOMME(0) <= VAL1(0) xor VAL2(0);
    > C0 <= VAL1(0) and VAL2(0);
    >
    > SOMME(1) <= VAL1(1) xor VAL2(1) xor C0;
    > C1 <= (VAL1(1) and VAL2(1)) or (C0 and (Val1(1) or Val2(1)));
    >
    > SOMME(2) <= VAL1(2) xor VAL2(2) xor C1;
    > C2 <= (VAL1(2) and VAL2(2)) or (C1 and (Val1(2) or Val2(2)));
    >
    > SOMME(3) <= VAL1(3) xor VAL2(3) xor C2;
    > RETENUE <= (VAL1(3) and VAL2(3)) or (C2 and (Val1(3) or Val2(3)));
    >end ADD4_BOOL;


    This is a structural description of a ripple-carry adder.
    Although your VHDL looks correct, it is crazy to use VHDL like
    this. The whole point of an HDL is to allow you to AVOID this
    kind of dreary work.

    >It seems to me that the first one look like shorter but may allocate
    >more resources because of the many 5 bits "SIGNAL"


    It's OK. Any good synthesis tool will note that the most significant
    bit of the adder has two constant inputs '0' and only one variable
    input (carry from bit 3) - so it becomes a simple wire.

    >Am I right ?


    In principle, yes. In practice, synthesis will remove the unused
    logic.

    Good luck with your learning.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jul 22, 2005
    #2
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  3. Jonathan Bromley a écrit :
    > On Wed, 20 Jul 2005 22:53:10 +0200, Pascal Peyremorte
    > <> wrote:
    >>[...]
    >>Am I right ?

    >
    >
    > In principle, yes. In practice, synthesis will remove the unused
    > logic.
    >
    > Good luck with your learning.


    Thank you very much for all that.

    Pascal
    Pascal Peyremorte, Jul 22, 2005
    #3
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