VHDL Case Statement

Discussion in 'VHDL' started by The Hath, Apr 27, 2007.

  1. The Hath

    The Hath

    Joined:
    Apr 27, 2007
    Messages:
    1
    Is it possible to have a case statement where it only changes state on the positive edge of the clock? For instance in the statement below, I only want A to be changed on the positive (rising) edge of num.

    case (num) is
    when '0' =>
    A<='0';
    when others =>
    A<=1;
    end case;

    For the when lines can I use:
    when '0 and event'
    or something like that?
    The Hath, Apr 27, 2007
    #1
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