Vhdl Cli bugs ??

Discussion in 'VHDL' started by aniket, Sep 27, 2003.

  1. aniket

    aniket Guest

    hi

    i am using vhdl cli with synopsys vss simulator ...
    i tried small eg in which a sync rom was implemented in vhdl
    and the test bench was in cli .
    a second program generated the address which was passed
    to the simulator using socket ...
    and the data read was passed back to the second program
    using sockets ....

    the cli routine was set to be event triggered on clk ...
    The setup worked fine for a fw initial run of few hundread clk cycles

    but when i give runs for longer duration there is a
    loss of sync asif the eval routine gets called multiple times
    in a single clock cycle ...

    has anyone experianced anything likethis ..
    can it be a bug ...in my setup using sockets etc...
    let me know if u need further details of my setup ...
    pls let me know ...
    till then i am finding out from myside using gdb ...

    regards
    aniket
     
    aniket, Sep 27, 2003
    #1
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