vhdl code for FIR Filter using wave-pipelining

[deepthi.reddy.912]

Hi,

I am doing a project on Asynchronous Wave-pipelined circuits using Xilinx FPGA.

I am using 4-tap FIR Filter for that.

I am implementing non-pipelining,pipelining and wave-pipeling on same filter separately and comparing the results for no. of slices used, frequency and power.

I am struck up at the vhdl code of the wave-pipeling and pipelining stages.

kindly help me how to modify the following non-pipelined FIR filter vhdl code to achieve pipelining and wave-pipeling separately.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fir_4_tab is
port (clk,rst:in std_logic;
data_in:in std_logic_vector(7 downto 0);
data_outut std_logic_vector(18 downto 0));
end fir_4_tab;

architecture fir_arch of fir_4_tab is
component shift_block
port (clk,rst:in std_logic;
data_in:in std_logic_vector( 7 downto 0);
data_outut std_logic_vector( 7 downto 0));
end component;

component ROM
port (clk,rst:in std_logic;
Addr :in std_logic_vector(3 downto 0);
rom_data : out std_logic_vector(7 downto 0));
end component;

component c_l_addr_16
PORT
(
x_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
ADD_OUT : OUT STD_LOGIC_VECTOR(16 DOWNTO 0));
END component;

component c_l_addr_17
PORT
(
x_in : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
ADD_OUT : OUT STD_LOGIC_VECTOR(17 DOWNTO 0));
END component;

component c_l_addr_18
PORT
(
x_in : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
ADD_OUT : OUT STD_LOGIC_VECTOR(18 DOWNTO 0));
END component;

component DFF_CLK
generic (data_length: positive:=16);
port (rst:in std_logic;
clk:in std_logic;
D_in:in std_logic_vector(data_length -1 downto 0);
Q_outut std_logic_vector(data_length-1 downto 0));
end component;

-------------------------------------------------------------
signal tab_1:std_logic_vector(7 downto 0);
signal tab_2:std_logic_vector(7 downto 0);
signal tab_3:std_logic_vector(7 downto 0);
signal tab_4:std_logic_vector(7 downto 0);

signal rom_addr_0:std_logic_vector(3 downto 0);
signal rom_addr_1:std_logic_vector(3 downto 0);
signal rom_addr_2:std_logic_vector(3 downto 0);
signal rom_addr_3:std_logic_vector(3 downto 0);
signal rom_addr_4:std_logic_vector(3 downto 0);
signal rom_addr_5:std_logic_vector(3 downto 0);
signal rom_addr_6:std_logic_vector(3 downto 0);
signal rom_addr_7:std_logic_vector(3 downto 0);

signal rom_out_1:std_logic_vector(7 downto 0);
signal rom_out_2:std_logic_vector(7 downto 0);
signal rom_out_3:std_logic_vector(7 downto 0);
signal rom_out_4:std_logic_vector(7 downto 0);
signal rom_out_5:std_logic_vector(7 downto 0);
signal rom_out_6:std_logic_vector(7 downto 0);
signal rom_out_7:std_logic_vector(7 downto 0);
signal rom_out_8:std_logic_vector(7 downto 0);

signal adder_1 :std_logic_vector(16 downto 0);
signal adder_2 :std_logic_vector(16 downto 0);
signal adder_3 :std_logic_vector(16 downto 0);
signal adder_4 :std_logic_vector(16 downto 0);

--signal d_adder_1 :std_logic_vector(16 downto 0);
--signal d_adder_2 :std_logic_vector(16 downto 0);
--signal d_adder_3 :std_logic_vector(16 downto 0);
--signal d_adder_4 :std_logic_vector(16 downto 0);
--

signal adder_5 :std_logic_vector(17 downto 0);
signal adder_6 :std_logic_vector(17 downto 0);

signal adder_7 :std_logic_vector(18 downto 0);

--signal d_adder_5 :std_logic_vector(17 downto 0);
--signal d_adder_6 :std_logic_vector(17 downto 0);


signal shift_1:std_logic_vector(15 downto 0);
signal shift_2:std_logic_vector(15 downto 0);
signal shift_3:std_logic_vector(15 downto 0);
signal shift_4:std_logic_vector(15 downto 0);
signal shift_5:std_logic_vector(15 downto 0);
signal shift_6:std_logic_vector(15 downto 0);
signal shift_7:std_logic_vector(15 downto 0);
signal shift_8:std_logic_vector(15 downto 0);

--signal d_shift_1:std_logic_vector(15 downto 0);
--signal d_shift_2:std_logic_vector(15 downto 0);
--signal d_shift_3:std_logic_vector(15 downto 0);
--signal d_shift_4:std_logic_vector(15 downto 0);
--signal d_shift_5:std_logic_vector(15 downto 0);
--signal d_shift_6:std_logic_vector(15 downto 0);
--signal d_shift_7:std_logic_vector(15 downto 0);
--signal d_shift_8:std_logic_vector(15 downto 0);

begin
----------------------------------------------------------------
stage_1:shift_block port map(clk,rst,data_in,tab_1) ;
stage_2:shift_block port map(clk,rst,tab_1,tab_2) ;
stage_3:shift_block port map(clk,rst,tab_2,tab_3) ;
stage_4:shift_block port map(clk,rst,tab_3,tab_4) ;
------------------------------------------------------------------------
rom_addr_0<=tab_4(0) & tab_3(0) & tab_2(0) & tab_1(0);
rom_addr_1<=tab_4(1) & tab_3(1) & tab_2(1) & tab_1(1);
rom_addr_2<=tab_4(2) & tab_3(2) & tab_2(2) & tab_1(2);
rom_addr_3<=tab_4(3) & tab_3(3) & tab_2(3) & tab_1(3);
rom_addr_4<=tab_4(4) & tab_3(4) & tab_2(4) & tab_1(4);
rom_addr_5<=tab_4(5) & tab_3(5) & tab_2(5) & tab_1(5);
rom_addr_6<=tab_4(6) & tab_3(6) & tab_2(6) & tab_1(6);
rom_addr_7<=tab_4(7) & tab_3(7) & tab_2(7) & tab_1(7);

rom_1:ROM port map (clk,rst,rom_addr_0,rom_out_1);
rom_2:ROM port map (clk,rst,rom_addr_1,rom_out_2);
rom_3:ROM port map (clk,rst,rom_addr_2,rom_out_3);
rom_4:ROM port map (clk,rst,rom_addr_3,rom_out_4);
rom_5:ROM port map (clk,rst,rom_addr_4,rom_out_5);
rom_6:ROM port map (clk,rst,rom_addr_5,rom_out_6);
rom_7:ROM port map (clk,rst,rom_addr_6,rom_out_7);
rom_8:ROM port map (clk,rst,rom_addr_7,rom_out_8);
----------------------------------------------------------------------


-----------------------------------------------------------------------
shift_1<="0000000" & rom_out_1 & '0';
shift_2<="000000" & rom_out_1 & "00";
shift_3<="00000" & rom_out_1 & "000";
shift_4<="0000" & rom_out_1 & "0000";
shift_5<="000" & rom_out_1 & "00000";
shift_6<="00" & rom_out_1 & "000000";
shift_7<="0" & rom_out_1 & "0000000";
shift_8<= rom_out_1 & "00000000";
------------------------------------------------------------------------
--DFF_1 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_1,d_shift_1);
--DFF_2 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_2,d_shift_2);
--DFF_3 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_3,d_shift_3);
--DFF_4 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_4,d_shift_4);
--DFF_5 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_5,d_shift_5);
--DFF_6 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_6,d_shift_6);
--DFF_7 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_7,d_shift_7);
--DFF_8 FF_CLK generic map (data_length => 16) port map(rst,clk,shift_8,d_shift_8);
------------------------------------------------------------------------
add_1:c_l_addr_16 port map(shift_1,shift_2,adder_1);
add_2:c_l_addr_16 port map(shift_3,shift_4,adder_2);
add_3:c_l_addr_16 port map(shift_5,shift_6,adder_3);
add_4:c_l_addr_16 port map(shift_7,shift_8,adder_4);
------------------------------------------------------------------------
--DFF_9 FF_CLK generic map (data_length => 17) port map(rst,clk,adder_1,d_adder_1);
--DFF_10 FF_CLK generic map (data_length => 17) port map(rst,clk,adder_2,d_adder_2);
--DFF_11 FF_CLK generic map (data_length => 17) port map(rst,clk,adder_3,d_adder_3);
--DFF_12 FF_CLK generic map (data_length => 17) port map(rst,clk,adder_4,d_adder_4);
-------------------------------------------------------------------------
add_5:c_l_addr_17 port map(adder_1,adder_2,adder_5);
add_6:c_l_addr_17 port map(adder_3,adder_4,adder_6);
---------------------------------------------------------------------------
--DFF_13 FF_CLK generic map (data_length => 18) port map(rst,clk,adder_5,d_adder_5);
--DFF_14 FF_CLK generic map (data_length => 18) port map(rst,clk,adder_6,d_adder_6);
-----------------------------------------------------------------------------
add_7:c_l_addr_18 port map(adder_5,adder_6,data_out);
--------------------------------------------------------
--DFF_15 FF_CLK generic map (data_length => 19) port map(rst,clk,adder_7,data_out);
--------------------------------------------------------------------------------
end fir_arch;