vhdl coding for fetching into memory

Discussion in 'VHDL' started by shweta, Aug 28, 2008.

  1. shweta

    shweta Guest

    as there is readmemh in verilog to read a file and put it into
    memory... is there any relevant thing in VHDL which can do this.
     
    shweta, Aug 28, 2008
    #1
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  2. shweta wrote:
    > as there is readmemh in verilog to read a file and put it into
    > memory... is there any relevant thing in VHDL which can do this.


    Not exactly.
    I would declare and use a constant array something like:

    type small_rom is array (0 to 2**a_length -1)
    of unsigned(d_length-1 downto 0);
    constant this_rom : small_rom :=
    (
    0 => x"00",
    1 => x"01",
    2 => x"02",
    3 => x"04",
    4 => x"08",
    5 => x"10",
    6 => x"20",
    7 => x"40",
    98 => x"AA",
    99 => x"BB",
    others => x"42"
    );

    -- Mike Treseler
     
    Mike Treseler, Aug 28, 2008
    #2
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  3. shweta wrote:
    > as there is readmemh in verilog to read a file and put it into
    > memory... is there any relevant thing in VHDL which can do this.


    It depends on the synthesizer. Here is a snippet from an example in the
    XST user's guide that initializes a ROM from a file. I haven't tried it
    myself:

    architecture syn of rams_20c is
    type RamType is array(0 to 63) of bit_vector(31 downto 0);
    impure function InitRamFromFile (RamFileName : in string) return
    RamType is
    FILE RamFile : text is in RamFileName;
    variable RamFileLine : line;
    variable RAM : RamType;
    begin
    for I in RamType'range loop
    readline (RamFile, RamFileLine);
    read (RamFileLine, RAM(I));
    end loop;
    return RAM;
    end function;
    signal RAM : RamType := InitRamFromFile("rams_20c.data");
    begin...

    -Kevin
     
    Kevin Neilson, Aug 28, 2008
    #3
  4. shweta

    gramador Guest

    On 28 Aug., 11:04, shweta <> wrote:
    > as there is readmemh in verilog to read a file and put it into
    > memory... is there any relevant thing in VHDL which can do this.


    The memory blocks you instantiate for Altera fpga have a generic
    option where you can specify a init file (hex or mif format).
    I'm pretty sure that I've seen this for Xilinx too.
    Of course, this is not VHDL related. But perhaps what you want.

    Regards
    Torsten
     
    gramador, Sep 2, 2008
    #4
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