[VHDL] Comparing entity and component declarations

Discussion in 'VHDL' started by M.D. van de Burgwal, Oct 6, 2004.

  1. Assume I have the next entity description in file A:
    ENTITY comp1 IS
    port (A : IN std_logic; B: OUT std_logic);
    END comp1;

    I want to use the entity in another file B, so I declare a component:
    COMPONENT comp1
    port (A : IN std_logic; B: OUT std_logic);
    END COMPONENT;

    Next, I find a bug in the original entity comp1 in file A and I need to
    change some port definition:
    ENTITY comp1 IS
    port (A : IN std_logic_vector(1 downto 0); B: OUT std_logic);
    END comp1;

    When I do not change the component declaration in file B, ModelSim (version
    SE 5.7d) will compile file B without any changed ports.
    Is there any way to make ModelSim compare the original entity declaration
    and the component instantation, returning an error when something has
    changed? Or are there workarounds?

    Thx,
    Marcel van de Burgwal
     
    M.D. van de Burgwal, Oct 6, 2004
    #1
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  2. M.D. van de Burgwal wrote:
    > When I do not change the component declaration in file B, ModelSim
    > (version SE 5.7d) will compile file B without any changed ports.
    > Is there any way to make ModelSim compare the original entity declaration
    > and the component instantation, returning an error when something has
    > changed? Or are there workarounds?


    If by compile you mean vcom, then no. During the compile of a VHDL file, the
    components are taken at face value, and are only compared to their
    instantiations. Whether the component matches the entity is only performed
    when the design is elaborated in vsim, because only at _that_ time do you
    tell the tool which design unit is actually instantiated in that particular
    location.

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Oct 6, 2004
    #2
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  3. M.D. van de Burgwal

    Guitarman Guest

    "M.D. van de Burgwal" <> wrote in message news:<ck0efv$fq5$>...
    > Assume I have the next entity description in file A:
    > ENTITY comp1 IS
    > port (A : IN std_logic; B: OUT std_logic);
    > END comp1;
    >
    > I want to use the entity in another file B, so I declare a component:
    > COMPONENT comp1
    > port (A : IN std_logic; B: OUT std_logic);
    > END COMPONENT;
    >
    > Next, I find a bug in the original entity comp1 in file A and I need to
    > change some port definition:
    > ENTITY comp1 IS
    > port (A : IN std_logic_vector(1 downto 0); B: OUT std_logic);
    > END comp1;
    >
    > When I do not change the component declaration in file B, ModelSim (version
    > SE 5.7d) will compile file B without any changed ports.
    > Is there any way to make ModelSim compare the original entity declaration
    > and the component instantation, returning an error when something has
    > changed? Or are there workarounds?
    >
    > Thx,
    > Marcel van de Burgwal



    I don't believe so. I would actually find it scary if ModelSim would
    edit my files automatically. Xilinx Webpack will automatically
    generate a testbench template containing the correct port
    instantiation, but that's not what you want.
     
    Guitarman, Oct 6, 2004
    #3
  4. M.D. van de Burgwal wrote:

    > When I do not change the component declaration in file B, ModelSim (version
    > SE 5.7d) will compile file B without any changed ports.
    > Is there any way to make ModelSim compare the original entity declaration
    > and the component instantation, returning an error when something has
    > changed?


    Using a configuration declaration will cause the compiler issue an error
    during the compilation of the configuration.

    CONFIGURATION conf_name OF toplevel_entity IS
    FOR arch_name_toplevel
    FOR ALL: comp1
    USE ENTITY work.comp1(arch_name_comp1);
    END FOR;
    END;
    END CONFIGURATION conf_name;

    Paul.
     
    Paul Uiterlinden, Oct 7, 2004
    #4
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