vhdl complex memory addressing

Discussion in 'VHDL' started by Alex, Jan 31, 2006.

  1. Alex

    Alex Guest

    Hi to all,
    I'm new in vhdl. My problem is that I have to address a memory composed
    of 2 banks, M muxes, N pages and K words.

    The address is 15 bits long:

    14 13 11 10 9 8 0
    -----------------------------------------------------------------------------
    | BANK | MUX | PAGE | WORD |
    -----------------------------------------------------------------------------

    My question is: how can I define the structure to write/read a word?
    I think I must declare a sort of array of arrays of arrays... but in
    the web and in my book I have found only examples of simple memory with
    a single type declaration like this:

    type ram_type is array (0 to 255) of std_logic_vector(15 downto 0);

    Thanks,
    Alex.
     
    Alex, Jan 31, 2006
    #1
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  2. Alex

    Guest

    > My problem is that I have to address a memory composed
    > of 2 banks, M muxes, N pages and K words.


    You're not really giving us enough information to help.... You need to
    provide details on how the REAL RAM handles it's paging etc. How wide
    is your RAM? Timings etc.

    > My question is: how can I define the structure to write/read a word?


    Erm, you cannot. You have to determine what I/O your memory has
    (address, data, write strobe, chip select etc.) then any requirements
    of timing between asserting your address and the data being valid etc.
    You may have to create a state-machine to do the reads and writes as
    chances they may be multi-cycle.

    > type ram_type is array (0 to 255) of std_logic_vector(15 downto 0);


    This is a description of a register array, not a RAM/memory. Used for
    small internal usage and perhaps used as part of a behavioural model of
    real RAMs
     
    , Jan 31, 2006
    #2
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  3. Alex

    Alex Guest

    Hi,
    thank you... yes, I have post too few data.

    I have defined the entity of that memory and now the problem is to
    describe a behavioural description.

    This is the entity:

    entity memory is

    generic (
    logbanks : integer := 1; -- log2 of banks
    logpages : integer := 3; -- log2 of pages
    logmuxes : integer := 2; -- log2 of muxes
    logwords : integer := 9; -- log2 of words
    addsize : integer := 15; --
    logbanks+logpages+logmux+logwords
    datasize : integer := 16);

    port (
    datain : in std_logic_vector(datasize-1 downto 0);
    dataout : out std_logic_vector(datasize-1 downto 0);
    address : in std_logic_vector(addsize-1 downto 0);
    ck : in std_logic; -- clock
    rst : in std_logic; -- asynchronous reset
    ce : in std_logic; -- chip enable
    rw : in std_logic); -- rw ='1'=>read, rw
    ='0'=>write

    end memory;
     
    Alex, Jan 31, 2006
    #3
  4. Alex wrote:

    > I'm new in vhdl. My problem is that I have to address a memory composed
    > of 2 banks, M muxes, N pages and K words.


    Sounds more like a homework problem,
    than a real memory device.

    > My question is: how can I define the structure to write/read a word?


    I would design a synchronous controller to
    implement all of the read and write cycles
    I cared about from the device data sheet.

    > type ram_type is array (0 to 255) of std_logic_vector(15 downto 0);


    A type like that might be used to infer
    an internal block ram or register bank.

    -- Mike Treseler
     
    Mike Treseler, Jan 31, 2006
    #4
  5. Alex

    Guest

    That still is not enough information. Real memories usually have delays
    between asserting address and data being valid. Even more so with
    memories with pages and banks. Find out what the behaviour is.
     
    , Feb 2, 2006
    #5
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