VHDL component for counting leading zeroes

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hello,

What would be the best way (from fast synthesis point of view) to calculate the amount of leading zeroes from substraction result of two bit vectors without doing the actual substraction.


Is there a way to implement it in more convenient way than described below:

signal A : std_logic_vector(9 downto 0);
signal B : std_logic_vector(9 downto 0);

result <= A - B;


Priority coded comparison (compare bit by bit starting from MSB):

if result(9) = '0' then

elsif result(8) = '0' then

elsif result(7) = '0' then....

############################

I'm after a solution like below where the amount of leading zeroes is received from some arithmetic and then compared directly with multiplexer

lead_zeros <= A xor nor and not B ?

case lead_zeros is
when 0 =>
when 1 =>
when 2 =>
 

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