VHDL connecting block different timing

Discussion in 'VHDL' started by niyander, Jun 25, 2010.

  1. niyander

    niyander Guest

    hello,

    i have created two vhdl designs, a floating point adder and a binary
    to floating point conversion unit. I wish to connect both the designs,
    but when i simulate both the design in modelsim, floating point adder
    takes 8ns and binary to floating point conversion unit takes 6ns to
    process completely, now if i connect both of them together (input
    flows first into binary to floating point unit and after it to the
    adder unit), now my question is if i connect them will they be working
    properly without any timing issue for many inputs one after another
    and not skip any input? and if not then how can i connect them to work
    synchronously. I would really appreciate if some one can help me.

    I have consulted this with one of my friend and he suggested me to use
    latch/register design, can any one point me to an example of
    connecting blocks using latch/register method in vhdl.

    thanks
    niyander
     
    niyander, Jun 25, 2010
    #1
    1. Advertising

  2. niyander

    KJ Guest

    On Jun 25, 11:02 am, niyander <> wrote:
    > now my question is if i connect them will they be working
    > properly without any timing issue for many inputs one after another
    > and not skip any input?


    - For function verification, I would suggest writing a simulation
    testbench to test that your design is working properly.

    - For timing verification, I would suggest that you specify the input
    setup time, clock
    to output delay, propogation delay and clock cycle requirements to
    your synthesis tool and then verify that the static timing analysis
    report that gets generated shows no errors.

    You haven't provide any useful information for anybody in this group
    to give you even a weak 'yes' or 'no' answer to your question. It's
    your design after all.

    > and if not then how can i connect them to work
    > synchronously. I would really appreciate if some one can help me.
    >


    I would look for some good VHDL textbooks.

    > I have consulted this with one of my friend and he suggested me to use
    > latch/register design, can any one point me to an example of
    > connecting blocks using latch/register method in vhdl.
    >


    As well as some digital design textbooks.

    KJ
     
    KJ, Jun 25, 2010
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Mike Treseler
    Replies:
    5
    Views:
    753
    Okashii
    Sep 13, 2005
  2. morrell
    Replies:
    1
    Views:
    965
    roy axenov
    Oct 10, 2006
  3. afd
    Replies:
    1
    Views:
    8,363
    Colin Paul Gloster
    Mar 23, 2007
  4. lozza_c

    VHDL timing problem

    lozza_c, Oct 18, 2008, in forum: VHDL
    Replies:
    0
    Views:
    600
    lozza_c
    Oct 18, 2008
  5. timinganalyzer
    Replies:
    1
    Views:
    888
    Gabor
    Nov 19, 2009
Loading...

Share This Page