VHDL correspondance of Verilog construct

[Floresita]

Hi,

following question:


Verilog-code:

always@(posedge clk)
if (reset)
number <= 3'd 0;
else if(valid) begin
....
show = (number >= 3);
...
end


How are these Verilog constructs described in VHDL ?

Thank you.

Rgds

 

[Kai Harrekilde-Petersen]

Hi,

following question:


Verilog-code:

always@(posedge clk)
if (reset)
number <= 3'd 0;
else if(valid) begin
....
show = (number >= 3);
...
end


How are these Verilog constructs described in VHDL ?

process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
number <= (others => '0');
else
...
end if;
end if;
end process;

Note that you get a synchronous reset in your design above.


Regards,


Kai

 

[fe]

Verilog-code:

always@(posedge clk)
if (reset)
number <= 3'd 0;
else if(valid) begin
....
show = (number >= 3);
...
end

The implementation in VHDL depend on the type of each signals/ports.
Example:
if reset is a std_logic input port
and number is an unsigned(2 downto 0) signal
and valid is a boolean signal
and I suppose that show is only use inside the always block (use of blocking
assignment inside a clocked always block generate race condition if read
outside)
then

VHDL code

process(clk)
variable show : boolean;
begin
if rising_edge(clk) then
if reset = '1' then
number <= (others => '0');
elsif valid then -- note the difference between a boolean (valid) and a
std_logic (reset)
....
show := (number >= 3);
...
end if;
end if;
end process;

regards
fe

 

[Oggie]

Hi,

following question:


Verilog-code:

always@(posedge clk)
if (reset)
number <= 3'd 0;
else if(valid) begin
....
show = (number >= 3);
...
end


How are these Verilog constructs described in VHDL ?

Thank you.

Rgds

Here is the answer:

signal clk, reset, valid, show : std_logic;
signal number : std_logic_vector(2 downto 0);

process(clk)
begin
if rising_edge(clk) then
if(reset = '1') then
number <= (others => '0');
else
if(valid = '1') then
......
if(number >= "011") then
show <= '1';
else
show <= '0';
end if;
......
end if;
end if;
end if;
end process;

Cheers!
Oggie