VHDL for add/subtract

[clarken]

Hi all , i am new here.

I have got one question about the code for add and sub. Below is my code , but it can not work with the subtract arithmetic. Anyone knew what's wrong , please let me know , or anyone have the standard code for the substraction , please also let me know. Thank a lot


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity addsub is
port(
a,b : in std_logic_vector(7 downto 0);
ctrl : in std_logic;
r : out std_logic_vector(7 downto 0)
);
end addsub;

architecture subtraction of addsub is
signal src0,src1,sum : signed(7 downto 0);
signal cin : signed( 0 downto 0);
begin
src0 <= signed(a);
src1 <= signed(b)when ctrl = '0' else
signed(not b);
cin <= "0" when ctrl = '0' else
"1";
sum <= src0 + src1 + cin ;
r <= std_logic_vector(sum);
end subtraction;


I take 20 -10 , it give me 8 , i dun know why.

Thank a lot