VHDL for FPGA VME Slave

Discussion in 'VHDL' started by Colin Jackson, Aug 15, 2003.

  1. I'm working on a FPGA that is to have a few R/W registers on a VME bus.

    Anybody have some VHDL code they would like to share?

    If I use your ideas then your name will forever be in lights!

    Thanks!
     
    Colin Jackson, Aug 15, 2003
    #1
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  2. "Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in
    message news:p...
    > I'm working on a FPGA that is to have a few R/W registers on a VME bus.
    >
    > Anybody have some VHDL code they would like to share?
    >
    > If I use your ideas then your name will forever be in lights!


    Be very, very afraid.

    VME was defined as an *asynchronous* protocol to keep it
    independent of any CPU's clock. Consequently, any VME
    interface needs to be sensitive to EDGES on several different
    strobe signals (*DS0, *DS1, *AS and several others). I think
    you can do a reasonable job if you are prepared to oversample
    all the strobes with a clock of about 80MHz or faster, but
    a direct (asynch) implementation in FPGA would be horrible.

    Once you've coped with that asynch-strobes nonsense, the main
    remaining problem is performance. Given that you're only
    accessing a few registers, speed may not be a major problem.
    If this is so, the rest of the task is comparatively easy -
    just a matter of reading the fine print carefully, so that
    you don't get confused about address modifiers, word
    widths and burst transfers.

    Finally, be careful about electrical specs. VME was defined
    around a particular set of LSTTL devices (74LS641-1 bidi
    buffers, and a few others). Output drivers need to be able
    to sink 64mA, and be 5V-tolerant, to meet the specs. 74F543
    bidi latch/buffer chips are your friends here, if you can
    still get 'em.

    Enjoy!
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Aug 18, 2003
    #2
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  3. Have a look to :

    http://schwick.home.cern.ch/schwick/muctpi/FPGAdocu/LIB/VMELIB/index-long.html

    It seem a well organized job (not mine).



    On Fri, 15 Aug 2003, Colin Jackson wrote:

    > I'm working on a FPGA that is to have a few R/W registers on a VME bus.
    >
    > Anybody have some VHDL code they would like to share?
    >
    > If I use your ideas then your name will forever be in lights!
    >
    > Thanks!
    >
    >
    >
     
    Tullio Grassi, Aug 19, 2003
    #3
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