vhdl for implementing pre-fetch and an instruction cache

Discussion in 'VHDL' started by Eqbal Z, Nov 5, 2003.

  1. Eqbal Z

    Eqbal Z Guest

    Hi,

    I am trying to implement a 4 word (64 bit) pre-fetch queue and an
    instruction cache (4 x 64) to a 16 bit 5 stage pipeline processor. I
    have no idea where to begin, as I am very new to vhdl. I have done
    some vhdl coding like prior to this I added data forwarding to the
    pipeline processor etc.

    Can someone help me with some simple description on what I should look
    at doing?
    I guess I have to start with thiking about what inputs and outputs I
    would want and then go onto what do each of these units do with these
    input and outputs. I am kind of stuck here.

    The code that I already have is a 5 stage pipeline processor with
    interface to a ROM (which now needs to interface with i-cache).
    Eqbal Z, Nov 5, 2003
    #1
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  2. Eqbal Z a écrit :
    > Hi,
    >
    > I am trying to implement a 4 word (64 bit) pre-fetch queue and an
    > instruction cache (4 x 64) to a 16 bit 5 stage pipeline processor. I
    > have no idea where to begin, as I am very new to vhdl. I have done
    > some vhdl coding like prior to this I added data forwarding to the
    > pipeline processor etc.
    >
    > Can someone help me with some simple description on what I should look
    > at doing?
    > I guess I have to start with thiking about what inputs and outputs I
    > would want and then go onto what do each of these units do with these
    > input and outputs. I am kind of stuck here.
    >
    > The code that I already have is a 5 stage pipeline processor with
    > interface to a ROM (which now needs to interface with i-cache).


    You could have a look at LEON (http://www.gaisler.som/). It will give you an
    example of VHDL RTL model of a Sparc V8, including caches.

    Regards,
    --
    Renaud Pacalet, GET/ENST/COMELEC/LabSoC
    Institut Eurecom BP 193, 2229 route des Cretes
    F-06904 Sophia-Antipolis Cedex
    Tel : +33 (0) 4 9300 2770
    Fax : +33 (0) 4 9300 2627
    Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/
    Renaud Pacalet, Nov 6, 2003
    #2
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  3. Eqbal Z

    Eqbal Z Guest

    Renaud Pacalet <> wrote in message news:<bod4i2$cqh$>...
    > Eqbal Z a écrit :
    > > Hi,
    > >
    > > I am trying to implement a 4 word (64 bit) pre-fetch queue and an
    > > instruction cache (4 x 64) to a 16 bit 5 stage pipeline processor. I
    > > have no idea where to begin, as I am very new to vhdl. I have done
    > > some vhdl coding like prior to this I added data forwarding to the
    > > pipeline processor etc.
    > >
    > > Can someone help me with some simple description on what I should look
    > > at doing?
    > > I guess I have to start with thiking about what inputs and outputs I
    > > would want and then go onto what do each of these units do with these
    > > input and outputs. I am kind of stuck here.
    > >
    > > The code that I already have is a 5 stage pipeline processor with
    > > interface to a ROM (which now needs to interface with i-cache).

    >
    > You could have a look at LEON (http://www.gaisler.som/). It will give you an
    > example of VHDL RTL model of a Sparc V8, including caches.
    >
    > Regards,


    I looked at the code there. And frankly it is too complicated for a
    beginner like me. I need something simpler.
    Anyways, I have started thinking about vhdl for prefetch and here is
    what I am planning to implement. My prefetch queue is 4 words long. So
    it has 4 instructions. I output the instructions based on the last two
    bits of the address I get from the cpu and on the last iteration (i.e.
    when last bits are 11) I also want to send a signal to the cache to
    send the next set of instructions). What do I do for the first time
    when prefetch is empty? Should I implement a hit/miss, valid bit thing
    for prefetch queue as well?

    As for the instruction cache, I am declaring a record to contain the
    valid bit, the tag and the instructions (cache line) and then I will
    have an array of the record (4 line cache). I am wondering now if I
    will always get a miss for cache since instruction address are going
    to be sequential (except for branches) and prefetch is consuming 4
    instructions at a time in any case?

    Anyhow I might post some code as I progress along.
    Eqbal Z, Nov 8, 2003
    #3
  4. Eqbal Z

    Eqbal Guest

    Ok, so I am trying to write code for prefetch and I am kind of stuck.
    What do I need to do when there is a branch? Do I need to bring in the
    branch enable line to prefetch and flush it? Or I was thinking about
    checking if present address is sequential with previous one, if not
    then assume its a branch?

    Here is a code I have written so far. Please remember that I know very
    little vhdl still. Any help is greatly appreciated:
    ---------------------------------------------------------------------
    use STD.standard.all;
    use STD.textio.all;
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity prefetch64 is
    port(
    CLK : in std_logic;
    CEN : in std_logic;
    A : in std_logic_vector(15 downto 0);
    iadsin : in std_logic;
    aout : out std_logic_vector(15 downto 0);
    iadsout : out std_logic;
    din : in std_logic_vector(63 downto 0);
    rdyin : in std_logic;
    irdy : out std_logic;
    Q : out std_logic_vector(15 downto 0));
    end prefetch64;

    architecture prefetch_arc of prefetch64 is
    -- declare signals
    signal line : std_logic_vector(63 downto 0);

    signal empty : boolean := true;

    --signal prev_addr : std_logic_vector(15 downto 0);
    begin
    process(clk)
    begin

    variable prev_addr : std_logic_vector(15 downto 0) :=
    "0000000000000000";

    if (prev_addr = "") then -- ? shall I compare the prev addr here?
    empty <= true;
    irdy <= '0';
    iadsout <= '1';
    else
    if (rdyin = '1') then
    if (empty) then
    line <= din;
    empty <= false;
    iadsout <= '0'; irdy <= '0';
    elsif (cen = '0') then
    if (empty) then
    irdy <= '0'; iadsout <= '1';
    else
    if (iadsin = '1') then
    case A(1 downto 0) is
    when "00" => -- send request to cache
    Q <= din(15 downto 0);
    irdy <= '1'; iadsout <= '0';
    when "01" =>
    --irdy <= '0';
    Q <= din(31 downto 16);
    irdy <= '1'; iadsout <= '0';
    when "10" =>
    --irdy <= '0';
    Q <= din(47 downto 32);
    irdy <= '1'; iadsout <= '0';
    when "11" =>
    --irdy <= '0';
    Q <= din(63 downto 48);
    irdy <= '1'; iadsout <= '0'; empty <= true;
    when others =>
    Q <= (others => 'Z');
    irdy <= '0'; iadsout <= '0';
    end case;
    end if;
    end if;
    end if;
    end if;
    end if;
    prev_addr := a;
    end process;
    end prefetch_arc;
    Eqbal, Nov 16, 2003
    #4
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