VHDL for PCB design?

Discussion in 'VHDL' started by self, Sep 30, 2009.

  1. self

    self Guest

    Hello All,

    I'm looking for a practical way to use VHDL as the design entry method
    for designing printed circuit boards. We have expensive schematic
    drawing tools at work but I tire of editing all those silly symbols
    and connecting them together. I'd much rather use an HDL for board
    design for all the same reasons people abandoned schematics for
    designing integrated circuits years ago.

    Really, all I need is a way to generated a netlist from some
    structural VHDL of my design. If I could get to and EDIF output I
    could probably read that into my PCB layout tool. It occured to me
    that perhaps I could trick a regular chip synthesis tool, say Synplify
    or XST, into making the netlist.

    Please share any ideas.

    Pete Dudley
    Albuquerque, NM, USA
     
    self, Sep 30, 2009
    #1
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  2. self wrote:

    > Really, all I need is a way to generated a netlist from some
    > structural VHDL of my design. If I could get to and EDIF output I
    > could probably read that into my PCB layout tool.


    I've had the same thought, as have others:
    http://groups.google.com/groups/search?q="vhdl netlist" for board layout

    The netlist could be entered in vhdl in theory,
    but real layout tools like allegro see netlists
    as outputs, not inputs.

    Most schematics with large parts look like netlists already.

    And do I really want to type in 500 port IDs and
    pin numbers for an fpga model at my normal 1% error rate?
    The layout guy can do it faster than I can
    and most of the parts are already done.

    > It occurred to me
    > that perhaps I could trick a regular chip synthesis tool, say Synplify
    > or XST, into making the netlist.


    Even if allegro would accept my vhdl synthesis netlist as source,
    I would still have to make or port map the
    allegro physical models for layout.

    > Please share any ideas.


    That's all I've got.

    -- Mike Treseler
     
    Mike Treseler, Oct 1, 2009
    #2
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  3. Mike Treseler <> writes:

    > I've had the same thought, as have others:


    Me too: http://tinyurl.com/y8p7ynv

    I've also been looking for a way to write the netlist in HDL rather
    than drawing schematics for PCB designs.

    Petter

    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Oct 1, 2009
    #3
  4. self

    Shannon Guest

    On Oct 1, 3:44 am, Petter Gustad <> wrote:
    > Mike Treseler <> writes:
    > > I've had the same thought, as have others:

    >
    > Me too:http://tinyurl.com/y8p7ynv
    >
    > I've also been looking for a way to write the netlist in HDL rather
    > than drawing schematics for PCB designs.
    >
    > Petter
    >
    > --
    > A: Because it messes up the order in which people normally read text.
    > Q: Why is top-posting such a bad thing?
    > A: Top-posting.
    > Q: What is the most annoying thing on usenet and in e-mail?


    Are you guys serious? I know I am going to get in trouble for
    responding to this on a VHDL group but...wow....come on.

    I can not imagine a more horrendous way of entering a schematic. I
    praised the day when PSpice went from text only netlist to graphical
    entry! I guess I'm too much of a hardware guy. Schematic entry
    brings with it tons of important design rules and checks. Not to
    mention I defy anyone to look at a VHDL text representation of a
    schematic and tell me what the circuit does. Most of us hardware guys
    can take one glance at a schematic and get a gist of what it's doing
    in an instant. I guess for ultra simple designs you could do it but
    for anything more complex it would be a diagnostic nightmare of the
    1st order.

    Shannon (preparing to get flamed to death)
     
    Shannon, Oct 1, 2009
    #4
  5. Shannon <> writes:

    > Are you guys serious? I know I am going to get in trouble for
    > responding to this on a VHDL group but...wow....come on.


    I'm much more effective instantiating, connecting wires, searching
    etc. using Emacs using HDL rather than drawing wires. Also I'm able to
    do simple simulations of the PCB as well (depending upon if I have
    models of the devices, or make my own mockups).

    I'm thinking mostly of simple digital designs where larger parts like
    processor, memory, FPGA, etc. are being instantiated. The story would
    be different for a low level analog design (since you mentioned
    PSpice).

    Of course I would need to be able to run my netlist through a design
    rule checker, etc. but I haven't seen anything witch supports this
    flow yet.

    > schematic and tell me what the circuit does. Most of us hardware guys
    > can take one glance at a schematic and get a gist of what it's doing


    For the designs I have in mind you would probably not be able to tell
    without having the source of the code running on the processor and the
    HDL for the FPGA...

    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Oct 1, 2009
    #5
  6. self

    Andy Guest

    I started doing FPGA design 20 years ago using schematics, and after
    initial reluctance, embraced the move to VHDL in the early 90's (I
    remember rejoicing about direct entity instantiation when it was
    introduced in VHDL'93). I had created recursive schematic
    implementations for parameterized symbols for adders, counters, shift
    registers, binary trees of gates, comparators, muxes, demuxes, etc.
    all done in schematics (using Valid GED, the precursor to Cadence
    Concept/DE-HDL), but it did not take long to gladly abandon all that
    for VHDL. I even had a trick for designing state machines in
    schematics, but it paled in comparison to what I could do with VHDL.

    But that was FPGA's, not boards...

    There is a huge difference in the nature of board level design vs ASIC/
    FPGA design. Board level design is necessarily about adding and
    connecting pre-defined components. While this is also true of ASIC/
    FPGA designs that primarily stitch together IP cores, ASIC/FPGA design
    also involves functional behavior independent of structure (RTL code).
    The big advance in ASIC/FPGA design from schematic to HDL was not in
    how easy it was to enter a netlist of primitives, but in how easy it
    was to specify a desired behavior, and let synthesis figure out how to
    build it. Until we have board level synthesis, we cannot expect a
    similar productivity improvement for board level design from utilizing
    HDL. Cadence introduced a "spreadsheet" board design entry tool a few
    years ago, that as far as I know went no-where. For backplane designs,
    etc. it was a god-send (lots of repetitive connections to multiple
    identical components), but for typical board level design, it did not
    give a significant advantage over schematic entry; it was too much
    like netlist entry.

    How hard it is to draw a schematic depends on what level of detail you
    need to show. If you can live with bus-wide pins on symbols, connected
    by a single "wire" on the schematic, (no discrete pin numbers shown),
    then a lot of the advantages of HDL entry are gone. Intelligent use of
    schematic hierarchy (depending on the tool's capability) gives you
    similar abilty to manage scale, complexity and reuse as you have in
    HDL.

    While the glorious part of a board design (hooking up this bus from
    this chip to that chip) is what most people "see", all the little
    "analog" connections between discrete resistors, capacitors, etc. that
    don't need to be named, give a significant boost to the efficiency of
    schematic entry. Even with named signals, the name is only specified
    once in a schematic (twice or more if it spans pages), rather than at
    least three times for a simple point to point connection (declaration,
    source port map, destination port map) in HDL. If I need to insert a
    resistor or buffer in the middle of a net, I can drop it into my
    schematic editor on top of the wire, and the tool immediately breaks
    the wire in two and connects it. In HDL, I'd need to declare another
    signal name, change one (or more) port map(s) to the new name, and add
    the new instance and port map connections manually. You never have to
    deal with these things in ASIC/FPGA design largely because the
    synthesis tool does it for you. Unfortunately we don't have those
    kinds of tools for board level design.

    With regards to creating symbols and the various map files required by
    schematic tools, the same types of information have to be entered in
    text in an HDL design, so there is no savings (and no semiautomated
    symbol generation tools) for HDL.

    When it comes to adding information to guide packaging, PWB layout and
    routing, a few simple mouse clicks or commands is all it takes to copy
    attributes from one net to another, or from one symbol to a whole set
    of symbols. Applying those attributes in HDL requires a lot more
    manual effort.

    And when it comes to understanding the large scale structure of a
    design, I find it easier to digest from a well drawn block diagram or
    top level of a hierarchical schematic than I do from a huge chunk of
    HDL.

    Andy
     
    Andy, Oct 1, 2009
    #6
  7. self

    backhus Guest

    On 30 Sep., 22:28, self <> wrote:
    > Hello All,
    >
    > I'm looking for a practical way to use VHDL as the design entry method
    > for designing printed circuit boards. We have expensive schematic
    > drawing tools at work but I tire of editing all those silly symbols
    > and connecting them together. I'd much rather use an HDL for board
    > design for all the same reasons people abandoned schematics for
    > designing integrated circuits years ago.
    >
    > Really, all I need is a way to generated a netlist from some
    > structural VHDL of my design. If I could get to and EDIF output I
    > could probably read that into my PCB layout tool. It occured to me
    > that perhaps I could trick a regular chip synthesis tool, say Synplify
    > or XST, into making the netlist.
    >
    > Please share any ideas.
    >
    >    Pete Dudley
    >    Albuquerque, NM, USA


    Hi Pete,
    sure, VHDL can be used to create netlists, and wether you want to edit
    them manually or with a schematic tool is up to your personal
    preferences.
    But what definitely won't work is to feed it into any FPGA synthesis
    tool and hope to get something useful for PCBs.
    Not even a useful design rule check, because FPGAs have different
    design rules than PCBs.

    So, while you can write a netlist in VHDL and expand it with
    attributes that arte useful for PCBs, you need a backend software that
    reads this file and does something useful with it.
    Even if you are going to convert it to EDIF, which is just another
    netlist format, it won't change anything. Even the converting tool has
    to be special to understand your VHDL attributes.

    e.g. You probably need a attribute to define wire_widths. No FPGA tool
    knows how to handle such an attribute, it is just meaningless for
    FPGAs.
    So even if you get some EDIF file from a FPGA tool you will loose
    all these attributes and the netlist is useless.

    So if you really want to use an existing PCB-tool that is able to read
    EDIF netlists, you probably need to write a vhdl2edif converter that
    creates an EDIF output that can be understood by your PCB-tool.

    Regards
    Eilert
     
    backhus, Oct 2, 2009
    #7
  8. Andy <> writes:

    > There is a huge difference in the nature of board level design vs ASIC/
    > FPGA design. Board level design is necessarily about adding and
    > connecting pre-defined components.


    I'm not saying that they are similar (I've been designing ASIC's since
    Verilog was a Gateway product and used HILO prior to that). I'm not
    talking about board level syntheis either.

    Still I think I can connect the predefined components quicker in Emacs
    than drawing the nets using a schematic editor. That's because I'm
    don't do it very often.

    > source port map, destination port map) in HDL. If I need to insert a
    > resistor or buffer in the middle of a net, I can drop it into my
    > schematic editor on top of the wire, and the tool immediately breaks
    > the wire in two and connects it. In HDL, I'd need to declare another
    > signal name, change one (or more) port map(s) to the new name, and add
    > the new instance and port map connections manually. You never have to


    I can do this in Emacs. I could write a (gensym) type function to
    generate unique netnames as well. One of the things I like better in
    Verilog than VHDL is the ability to declare a wire right in the middle
    of the logic, especially for little anonymous wires like these.

    The problem is that I haven't seen any tools which supports this type
    of flow.

    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Oct 2, 2009
    #8
  9. self

    Andy Guest

    Given enough time and effort, I'm convinced anything can be done in
    Emacs.

    You'd need:
    a tool to create/invoke "anonymous" signal names (I think this is a
    bad idea, see below.)
    a tool to easily create/invoke/manage attributes on signals, ports and
    component/entity instances.
    a tool to generate a (good) schematic drawing of your design (required
    output for most customers)
    a tool to manage/hide non-critical attributes to reduce clutter for
    review.
    a tool to do things like "find all the 1.1K 0603 resistors, and change
    them to 1.0K 0402 resistors"
    ....and many more I can't think of until I need it and don't have it.

    It's already done in a good schematic editor.

    Regarding "anonymous" wires: in a schematic, it is easy enough to see
    what pins a short, unnamed wire connects. In HDL, you have to find the
    name, and then find the matching name somewhere else. A schematic page
    uses two dimensions to allow you to place related things nearby, an
    HDL file has only one dimension. Reviewing connections by name in an
    hdl file is like panning around a schematic page with a postage stamp
    size viewer. Trust me, I've spent enough time tracking through
    netlists with machine-generated net names to know this ain't gonna be
    pretty.

    Cadence Design Entry HDL (FKA Concept-HDL) creates logical verilog and
    vhdl netlists from the schematic. Then the packager (assembler/
    netlister) uses the verilog netlist for its input to generate the
    physical netlist for board layout.

    So, theoretically you could code verilog and get a netlist to dump
    into Allegro for board layout and routing.

    Andy
     
    Andy, Oct 2, 2009
    #9
  10. Andy <> writes:

    > Given enough time and effort, I'm convinced anything can be done in
    > Emacs.
    >
    > You'd need:
    > a tool to create/invoke "anonymous" signal names (I think this is a
    > bad idea, see below.)
    > a tool to easily create/invoke/manage attributes on signals, ports and
    > component/entity instances.
    > a tool to generate a (good) schematic drawing of your design (required
    > output for most customers)
    > a tool to manage/hide non-critical attributes to reduce clutter for
    > review.
    > a tool to do things like "find all the 1.1K 0603 resistors, and change
    > them to 1.0K 0402 resistors"
    > ...and many more I can't think of until I need it and don't have it.
    >
    > It's already done in a good schematic editor.


    I can do most of these in Emacs expect for the schematic generation. I
    would use this flow for my own projects. For external customers this
    is probably not a suitable flow. I've never seen a good automatic
    schematic drawings (I've seen lots of Synopsys Design Compiler
    PostScript output which does not look that great).

    Keep in mind what I said earlier: "I'm thinking mostly of simple
    digital designs where larger parts like processor, memory, FPGA, etc.
    are being instantiated"

    > Regarding "anonymous" wires: in a schematic, it is easy enough to see
    > what pins a short, unnamed wire connects. In HDL, you have to find the
    > name, and then find the matching name somewhere else. A schematic page


    As I said, I prefer Verilog here since they can be right next to the
    instance in the file. I could write/generate something like this in my
    HDL netlist:

    processor cpu (.addr(addr),
    ....

    wire res109_to_addr_15;
    resistor r109 (.t1(res109_to_addr_15),.t2(addr[15]));
    .....

    Which I don't think is that bad.

    > size viewer. Trust me, I've spent enough time tracking through
    > netlists with machine-generated net names to know this ain't gonna be
    > pretty.


    I've also traced lots of post synthesis/PAR netlsts which have been
    hacked by BIST tools, by ATPG tools etc. But I have always used some
    programs or Emacs functions to trace the netlist. However, a flattened
    FPGA netlist with n000000N style netnames and u00000U style instance
    names connecting 80.000 LUT's is quite different than what I have in
    mind for a hand written HDL netlist at the top level.

    Last week I actually requested an EDIF netlist export from a board
    design engineer. I find it easier to trace signals in the EDIF file
    than browsing the 65 page PDF file containing the schematics. But
    since my favorite programming language is Common Lisp I have a toolbox
    of programs to search and transfer sexps which EDIF is based upon.
    However, I think I'm the only one that have this preference. We're all
    different.

    > Cadence Design Entry HDL (FKA Concept-HDL) creates logical verilog and
    > vhdl netlists from the schematic. Then the packager (assembler/
    > netlister) uses the verilog netlist for its input to generate the
    > physical netlist for board layout.
    >
    > So, theoretically you could code verilog and get a netlist to dump
    > into Allegro for board layout and routing.


    Theoretically you can probably do it in any PCB package as long as you
    can generate the right structure and use the right format for the
    netlist. The problem is that this is not a supported flow and it's not
    documented so you have to sort of reverse engieer the whole thing.

    Actually I did something similar in the late 80's. I wrote a program
    to flatten Verilog netlists and convert them into Dazix netlist format
    which was used to produce the PCB. In this case I was given some
    documentation for the Dazix netlist format. This was actually used for
    a design of a UNIX computer. However, I haven't done anything similar
    since.

    Petter
    --
    A: Because it messes up the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
     
    Petter Gustad, Oct 2, 2009
    #10
  11. self

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Search the net for "Altium designer" - seems like an interesting product for VHDL / PCB design (in combination)
    Jeppe
     
    jeppe, Oct 3, 2009
    #11
  12. self

    Andy Peters Guest

    On Oct 1, 7:12 am, Petter Gustad <> wrote:
    > Shannon <> writes:
    > > Are you guys serious?  I know I am going to get in trouble for
    > > responding to this on a VHDL group but...wow....come on.

    >
    > I'm much more effective instantiating, connecting wires, searching
    > etc. using Emacs using HDL rather than drawing wires. Also I'm able to
    > do simple simulations of the PCB as well (depending upon if I have
    > models of the devices, or make my own mockups).
    >
    > I'm thinking mostly of simple digital designs where larger parts like
    > processor, memory, FPGA, etc. are being instantiated. The story would
    > be different for a low level analog design (since you mentioned
    > PSpice).
    >
    > Of course I would need to be able to run my netlist through a design
    > rule checker, etc. but I haven't seen anything witch supports this
    > flow yet.
    >
    > > schematic and tell me what the circuit does.  Most of us hardware guys
    > > can take one glance at a schematic and get a gist of what it's doing

    >
    > For the designs I have in mind you would probably not be able to tell
    > without having the source of the code running on the processor and the
    > HDL for the FPGA...
    >
    > Petter


    I have some experience with this. A previous employer used a homebrew
    text "pinlist" as the design entry method. Emacs was the environment.
    It didn't use a standard HDL; instead, its language was literally a
    list of components and their pins. It was actually pretty smart. Each
    component was instantiated from a "library" and as such each had
    defined I/O pin types (power, in, out, bidir, passive, etc). Various
    emacs lisp things let you instantiate a component and connect up the
    ports in pretty quick fashion. It evolved over time to include
    submodules -- things like a processor, its cache memory, decoupling
    caps, etc etc could all be rolled up into a submodule and that
    submodule could be instantiated any number of times into a design.

    There was a substantial design-rule checking set-up, and from the
    pinlist you could generate a BOM (in a format that the purchasing
    people's system could understand) as well as a netlist acceptable by
    the PCB layout. It could even generate a text "schematic" (basically
    ASCII art).

    Being text based, it was very easy to search through a pinlist and
    find a particular net or component. Obviously source-code control
    would be very easy too but the person in charge did not see the
    benefit of this (arrrgh). Vendor lock-in was obviously not a problem,
    either.

    So the scheme actually worked pretty well. The major downsides were
    that the whole thing was homebrew, unstandardized and we basically
    depended on one person to maintain it. Documentation was basically non-
    existent and you never knew when something would change behind your
    back.

    -a
     
    Andy Peters, Oct 5, 2009
    #12
  13. self

    self Guest

    Thanks for all the replys. I'm glad to see there is some interest in
    this subject.

    The more I think about it the more compelling is the idea of using an
    HDL to define the board netlist. I think HDL entry becomes more
    valuable as the size of the design goes up.

    A few months ago, during a manic episode, I created an open source
    project at http://sourceforge.net/projects/pcbl/ I checked in some
    example source files as an example of what I was thinking about. I
    need to update those files because there are some syntax errors and
    the example board is too trivial to be of much use.

    My original idea was to use a project called Savant to parse the vhdl
    into the desired output netlist. I played around with Savant quite a
    bit but could not even get the example to run on my linux machine. I
    don't think Savant has much ongoing activity. Now I'm thinking that a
    program called ANTLR is the best way to parse VHDL for my purposes but
    this is also a daunting task. I've been warned by ANTLR users that
    VHDL is a particularly difficult grammar to parse.

    I believe it would be fairly easy to contrive a syntax for describing
    board netlists that would be very easy to parse into a netlist. I
    could probably write a small Perl script to do the parsing. I see that
    some of you guys have already been down this road. On the other hand,
    I want something that I could share with other designers for design
    review and design sharing. Also, to make the design readable I want
    hierarchy, generate loops, etc and these things already exist in
    standard HDL's.

    Another big plus with using a standard HDL is that you can use free
    FPGA tools to check syntax and view the connectivity of your design.
    I've used the Xilinx XST schematic viewer to look at my board netlist.
    You can traverse the hierarchy and see all the wiring. Also, in
    theory, you could simulate through your board design using any
    standard HDL simulator.

    Anyway, take a look into http://pcbl.svn.sourceforge.net/viewvc/pcbl/trunk/examples/pcb1/
    to see a simple example idea. I'll update the files so that they
    actually compile.

    I will report any actual success to this thread.

    Thanks,

    Pete
     
    self, Oct 10, 2009
    #13
  14. self

    self Guest

    I want to mention a couple of other things I have looked at. First of
    all, I tried using Xilinx XST to generate an edif netlist. XST
    generates a .ngc file and then you can use ngc2edif to make an edif
    file. The problem is that XST naturally strips off all the PCB related
    attributes that define pin numbers, etc.

    The other thing I'm looking at is JHDL (http://www.jhdl.org/). JHDL is
    a collection of java class libs that can be used to very efficiently
    describe a netlist for FPGA compilation. I've used this set of tools a
    few times to design logic for Xilinx Virtex-2 FPGA's and they are
    really neat. Everything is structural but since java is such a nice
    object oriented language you can reel out structure very quickly. The
    problem is that almost no hardware designers know anything about java
    syntax. The other problem is that I have forgotten all the java that I
    ever knew. In any case, I think a computer scientist could readily
    extend JHDL for board layout purposes.

    Pete
     
    self, Oct 10, 2009
    #14
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