vhdl generate related

Discussion in 'VHDL' started by pavithrashinde@gmail.com, Jun 14, 2006.

  1. Guest

    how do i give a component portmap statement inside a generate
    statement?
    i need to instantiate a component n no. of times
    the label is in the syntax so how i add that in the code?
     
    , Jun 14, 2006
    #1
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  2. Mike Treseler, Jun 14, 2006
    #2
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