vhdl guessing game

Discussion in 'VHDL' started by erman koseoglu, Nov 9, 2012.

  1. process(clkin)
    variable used : STD_LOGIC_VECTOR(1000 to 9999):= (others => '0');
    variable f : integer :=1000;
    variable t : integer :=1000;
    variable delayClock: integer :=0;
    variable tb,fb : STD_LOGIC_VECTOR(15 downto 0);
    begin
    if(rising_edge(clkin) and clkin='1') then
    --guessing mode
    if feedbackEntry_button='1' then
    tb:=bcdFromInteger(t);
    if (tb(3 downto 0)/=fb(3 downto 0)) then
    used(t):='1';
    end if;
    if(t<9999) then
    t:=t+1;
    end if;
    else
    t:=1000;
    fb:=bcdFromInteger(f);
    if(used(f)='1') then
    f:=f+1;
    end if;
    end if;

    --clock divider
    delayClock:=delayClock+1;
    if(delayClock>1500) then
    delayClock:=0;
    end if;
    if(delayClock=0) then
    myClock<=not myClock;
    end if;

    o<=f;
    end if;
    end process;

    this proces causes synthesis problem(it is stuck in infinite loop)

    what the program does(should do) is it guesses a 4 digit number "f" from solution set "used". When the feedbacketrybutton is pressed(and hold) program iterates from 1000 to 9999 (variable t) and compares the t with f. if their first digit(first 4 bit in bcd format) aren't same but should be(according to feedbackswitch(0)='1') then it eliminates t from solution set.

    why can't xilinx find a design to implement it and how can i improve my code.

    thanks in advance
    erman koseoglu, Nov 9, 2012
    #1
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  2. Le 09/11/2012 20:34, erman koseoglu a écrit :

    > this proces causes synthesis problem(it is stuck in infinite loop)


    You've left a lot to guess...
    Have you determined with absolute certitude that the problem lies in
    this very process ?
    You should post the architecture and entity too (at least so that we
    know which objects are signals and which are ports)
    What's the source for the bcdfrominteger function ?

    What is your targeted device ? Your code requires quite a lot of flip-flops

    Nicolas
    Nicolas Matringe, Nov 10, 2012
    #2
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  3. Hi,

    have you ever considered the HW your code shall create?

    You use no reset, so your code will only work if xilinx synthesise
    your initialisations as startup values after power up, I doubt this.


    On 9 Nov., 20:34, erman koseoglu <> wrote:
    >         process(clkin)
    >         variable used : STD_LOGIC_VECTOR(1000 to 9999):= (others => '0');

    variable f : integer :=1000;
    [..]
    >         begin
    >                 if(rising_edge(clkin) and clkin='1') then

    [..]
    >                                 if (tb(3 downto 0)/=fb(3 downto 0)) then
    >                                         used(t):='1';


    This means 9k Register.

    [..]
    >                                 if(used(f)='1') then
    >                                         f:=f+1;


    This requires somehow a mux with 9000 inputs -> ~9000 Mux2 building a
    tree of depth 14 getting clocked with Clkin.

    It is not impossible to synthesise this, but depending on the selected
    device and other constraints this numbers might be a lot of logic for
    that few lines of code. If you have more from these code portions,
    your easy blasting large devices.

    You defined f as integer without restriction, meaning, that your able
    to read and write on register used(2^31). YOu should limit the integer
    range in a way, that prevents indexing of unused bits.

    bye Thomas
    Thomas Stanka, Nov 13, 2012
    #3
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