vhdl hexa assignation

J

Julien Lochen

Hello,

I have a very very basic problem with the cadence VHDL compiler


signal test : std_logic_vector(3 downto 0);
....
test_jl_3 <= "1010"; => OK

test_jl_3 <= x"A"; => gives expecting an expression of type
STD_LOGIC_VECTOR 87[8.3] 93[8.4]

why ?

thanks

julien
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,482
Members
44,901
Latest member
Noble71S45

Latest Threads

Top