vhdl hexa assignation

Discussion in 'VHDL' started by Julien Lochen, Dec 5, 2008.

  1. Hello,

    I have a very very basic problem with the cadence VHDL compiler


    signal test : std_logic_vector(3 downto 0);
    ....
    test_jl_3 <= "1010"; => OK

    test_jl_3 <= x"A"; => gives expecting an expression of type
    STD_LOGIC_VECTOR 87[8.3] 93[8.4]

    why ?

    thanks

    julien
     
    Julien Lochen, Dec 5, 2008
    #1
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