VHDL integer signal in tri-state

Discussion in 'VHDL' started by Roberto Gallo, May 1, 2006.

  1. Hello all,

    I was wondering if is it possible to set a VHDL integer signal to
    something like a std_logic 'Z'...

    signal foo_s : integer

    It is possible to set:

    foo_s <= (something like tri-state)?

    My problem is that I have a fixed entity with integer ports and I would
    like to make then all tri-state when necessary.

    Thank you,
    Gallo
     
    Roberto Gallo, May 1, 2006
    #1
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  2. >I was wondering if is it possible to set a >VHDL integer signal to
    >something like a std_logic 'Z'...


    The question here is: What do you mean by "Tri State". Do you want to
    connect outputs to a bus like it is possible with std_logic values.

    If yes, you could interpret one integer value as "tri state", e.g.

    constant C_INTEGER_TRISTATE: integer:=integer'low;

    You have to define a resolution function of type "resolved_integer" and
    declare your bus as resolved_integer. Then you can connect integer
    typed outputs (and inputs) to this bus.

    type integer_vector is arrary (range <>) of integer;

    function resolved(res: integer_vector) return integer is -- resolved
    the maximum
    result: integer:=C_INTEGER_TRISTATE;
    begin
    for i in res'range loop
    if res(i)>result then
    result:=res(i);
    end if;
    end loop;
    return result;
    end;


    type resolved_integer is resolved_integer;

    signal bus: resolved_integer;

    (untested)

    Hubble.
     
    Reiner Huober, May 2, 2006
    #2
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  3. Reiner Huober wrote:
    >> I was wondering if is it possible to set a >VHDL integer signal to
    >> something like a std_logic 'Z'...

    >
    > The question here is: What do you mean by "Tri State". Do you want to
    > connect outputs to a bus like it is possible with std_logic values.
    >
    > If yes, you could interpret one integer value as "tri state", e.g.
    >
    > constant C_INTEGER_TRISTATE: integer:=integer'low;
    >
    > You have to define a resolution function of type "resolved_integer" and
    > declare your bus as resolved_integer. Then you can connect integer
    > typed outputs (and inputs) to this bus.
    >
    > type integer_vector is arrary (range <>) of integer;
    >
    > function resolved(res: integer_vector) return integer is -- resolved
    > the maximum
    > result: integer:=C_INTEGER_TRISTATE;
    > begin
    > for i in res'range loop
    > if res(i)>result then
    > result:=res(i);
    > end if;
    > end loop;
    > return result;
    > end;
    >
    >
    > type resolved_integer is resolved_integer;
    >
    > signal bus: resolved_integer;
    >
    > (untested)
    >
    > Hubble.
    >

    Thank you!
     
    Roberto Gallo, May 2, 2006
    #3
  4. Reiner Huober wrote:

    >> I was wondering if is it possible to set a >VHDL integer signal to
    >> something like a std_logic 'Z'...

    >
    > The question here is: What do you mean by "Tri State". Do you want to
    > connect outputs to a bus like it is possible with std_logic values.
    >
    > If yes, you could interpret one integer value as "tri state", e.g.
    >
    > constant C_INTEGER_TRISTATE: integer:=integer'low;
    >
    > You have to define a resolution function of type "resolved_integer" and
    > declare your bus as resolved_integer. Then you can connect integer
    > typed outputs (and inputs) to this bus.



    Another option is to use a record with one element being the integer and
    on element providing the driver strength (could be std_logic or a new
    defined type). Then it is also possible to define a resolution function
    for this record.
    The advantage: You don't loose integer values, that play the role of 'Z'
    and all the other possible states.

    Ralf
     
    Ralf Hildebrandt, May 2, 2006
    #4
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