VHDL ISA Bus Assignment Help

[d1430]

[FONT=&quot]For an introductory VHDL course, I have to code an ISA bus based off of 4 timing diagrams. I have very little VHDL knowledge and am not sure where to get started. Any advice or help is greatly appreciated. Here are the timing diagrams in PDF:[/FONT]
[FONT=&quot]http://www.mediafire.com/?3q6t3pgl4jhbb1t
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[FONT=&quot] Here is the assignment:[/FONT]
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[FONT=&quot]Information provided for this project:[/FONT]
[FONT=&quot]1. ISA Signal Descriptions[/FONT]
[FONT=&quot]2. ISA Timing Diagrams for the eight bit data bus[/FONT]
[FONT=&quot]Design VHDL code that represents the four timing diagrams that have been provided for[/FONT]
[FONT=&quot]this project:[/FONT]
[FONT=&quot]-8-Bit I/O Bus Cycles for Read and Write[/FONT]
[FONT=&quot]-8-Bit Memory Bus Cycles for Read and Write[/FONT]
[FONT=&quot]-I/O Conversion Bus Cycles for Read and Write[/FONT]
[FONT=&quot]i. This is for 16 bit transfers to and from 8 bit slaves[/FONT]
[FONT=&quot]-Memory Conversion Bus Cycles for Read and Write[/FONT]
[FONT=&quot]i. This is for 16 bit transfers to and from 8 bit slaves[/FONT]
[FONT=&quot]The ISA bus clock is eight mega-hertz (125 nanosecond)[/FONT]
[FONT=&quot]I recommend that you use a behaviorial model for your code.[/FONT]
[FONT=&quot]Demonstrate using a timing diagram (eight total diagrams for the report) that your design[/FONT]
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[FONT=&quot]Any help is hugely appreciated.[/FONT]