VHDL jpeg image processing

Discussion in 'VHDL' started by eem3kc@gmail.com, Jun 30, 2006.

  1. Guest

    Hi, I am a Master of UNIS and currently mapping c++ onto VHDL for image
    processing. I confused with jpeg format into VHDL that how to extract
    jpeg and how can I test it. Is it I put entities (rst, clk, data_in,
    datai(64 downto 0), data_out, datao(64 downto 0) and I do 3 blocks for
    IDCT, Dequantities, and Huff scanning and are they enough, hope anyone
    can help.
    Many thanks,
    KY
     
    , Jun 30, 2006
    #1
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  2. Ricardo Guest

    You may try to look the opencores.org for jpeg core. I think there are
    two of them. Xilinx has lots of appnotes about huffman, quantizer and
    other stuff. Google for it.

    The number of blocks you will need will depend on how you organize your
    code. This is a design pratice, each designer has its own or follow
    some convention. For example: your Huff has a small fifo inside, wich
    is another block (or entity).

    You do not seem a HDL experienced, so, I suggest some basics reading
    too, on both the language and Digital design. You won´t regret doing
    this.

    Regards,

    Ricardo

    escreveu:

    > Hi, I am a Master of UNIS and currently mapping c++ onto VHDL for image
    > processing. I confused with jpeg format into VHDL that how to extract
    > jpeg and how can I test it. Is it I put entities (rst, clk, data_in,
    > datai(64 downto 0), data_out, datao(64 downto 0) and I do 3 blocks for
    > IDCT, Dequantities, and Huff scanning and are they enough, hope anyone
    > can help.
    > Many thanks,
    > KY
     
    Ricardo, Jun 30, 2006
    #2
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  3. Guest

    Ricardo 寫é“:

    > You may try to look the opencores.org for jpeg core. I think there are
    > two of them. Xilinx has lots of appnotes about huffman, quantizer and
    > other stuff. Google for it.
    >
    > The number of blocks you will need will depend on how you organize your
    > code. This is a design pratice, each designer has its own or follow
    > some convention. For example: your Huff has a small fifo inside, wich
    > is another block (or entity).
    >
    > You do not seem a HDL experienced, so, I suggest some basics reading
    > too, on both the language and Digital design. You won´t regret doing
    > this.
    >
    > Regards,
    >
    > Ricardo
    >

    Thanks for your reply. Yes certainly I will not regret to do that. I
    have provided c++ code from my supervisor and there are several format
    I can choose for mapping, bitmap png, ppg etc. And now I have to do is
    to read too. So is that any book about image processing using VHDL??

    But jpeg is essentially common, and I want to target on. Anyway, saw my
    supervisor today and she asked me to look at read file functions and
    take lines I need to process only and try. See if this works also.

    Best regards,
    KY
     
    , Jul 6, 2006
    #3
  4. Ricardo Guest

    > Thanks for your reply. Yes certainly I will not regret to do that. I
    > have provided c++ code from my supervisor and there are several format
    > I can choose for mapping, bitmap png, ppg etc. And now I have to do is
    > to read too. So is that any book about image processing using VHDL??


    Google is your friend.

    >
    > But jpeg is essentially common, and I want to target on.Anyway, saw my


    try opencores, xilinx. Many of your blocks are there.

    > supervisor today and she asked me to look at read file functions and


    saerch for textio library.

    > take lines I need to process only and try. See if this works also.
    >
    > Best regards,
    > KY
     
    Ricardo, Jul 7, 2006
    #4
  5. Guest

    I can do up to this point where to load images into modelsim for a
    testbench. But I don't why the information load in a _ then it randomly
    skipped a few lines. I think it is some sort of readline problem or
    define input as : text. Anyone have this experience before???



    My code is :-

    library ieee;
    use ieee.std_logic_1164.all;
    use std.textio.all;
    use ieee.numeric_std.all;

    entity Loadimg is
    port(
    out_data_1 : out integer
    );end Loadimg;

    architecture fileio of loadimg is
    file in_img_1 : text;

    signal ch : character;
    signal int : integer;

    begin

    img1: process is
    variable ILine : Line;
    variable ch : character;

    begin
    file_open(in_img_1, "imagename", read_mode)


    while not endfile(in_img_1) loop
    readline(in_img_1, ILine_1);
    read(ILine_1, ch_1);
    -- converts character stored in char to
    -- integer (ASCII)
    int_1 <= character'pos (ch_1);

    out_data_1 <= int_1;

    wait for 5 ns;

    end loop;
    file_close(in_img_1);

    end process img1;
    end architecture fileio;



    For example .bmp format header should be BM†J.............ASCIIs.

    It reads out B for the 1st character, convert into integer is 99, then
    next should be M, but it straightly goes to colour data already 255
    let's say.

    I confused if I am using the right method to load a image into a
    testbench.
     
    , Jul 18, 2006
    #5
  6. Guest

    wrote:
    >
    > architecture fileio of loadimg is
    > file in_img_1 : text;
    >


    Above I mean
    architecture fileio of Loadimg is
     
    , Jul 18, 2006
    #6
  7. Guest

    I can do up to this point where to load images into modelsim for a
    testbench. But I don't why the information load in a _ then it randomly

    skipped a few lines. I think it is some sort of readline problem or
    define input as : text. Anyone have this experience before???


    My code is :-

    library ieee;
    use ieee.std_logic_1164.all;
    use std.textio.all;
    use ieee.numeric_std.all;

    entity Loadimg is
    port(
    o ut_data_1 : out integer
    );end Loadimg;

    architecture fileio of Loadimg is
    file in_img_1 : text;

    signal ch : character;
    signal int : integer;

    begin
    img1: process is
    variable ILine : Line;
    variable ch : character;

    begin
    file_open(in_img_1, "imagename", read_mode)
    while not endfile(in_img_1) loop
    readline(in_img_1, ILine);
    read(ILine, ch);
    -- converts character stored in char to
    -- integer (ASCII)
    int_1 <= character'pos (ch_1);
    out_data_1 <= int_1;

    wait for 5 ns;
    end loop;
    file_close(in_img_1);
    end process img1;
    end architecture fileio;



    For example .bmp format header should be BM†J.............ASCIIs.
    It reads out B for the 1st character, convert into integer is 99, then
    next should be M, but it straightly goes to colour data already 255
    let's say.
    I confused if I am using the right method to load a image into a
    testbench.
     
    , Jul 18, 2006
    #7
  8. wrote:

    > My code is :-
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use std.textio.all;


    > For example .bmp format header should be BM†J.............ASCIIs.
    > It reads out B for the 1st character, convert into integer is 99, then
    > next should be M, but it straightly goes to colour data already 255


    textio only works with text.
    Here's a binary file example:

    http://home.comcast.net/~mike_treseler/char_file.vhd

    -- Mike Treseler
     
    Mike Treseler, Jul 18, 2006
    #8
  9. bekhemali

    Joined:
    Nov 10, 2007
    Messages:
    1
    hi i am a bachelors student. i have to design and verify a jpeg compression/decompression core.
    i wanted to know which sofware can i use for VHDL description?
    can do it on visual studio C++ in c code and then map it on VHDL?
    what is a testbench? is it a software itself and when do we use it ?
    what software can we use for simulation?
    do i need to study VHDL for description?
     
    bekhemali, Nov 10, 2007
    #9
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