Marcus,
....
That is unfortunately true if you consider current VHDL. I heard that
some people are working on fitting PSL into VHDL assertions. At least
this is what I understood. Now with (possibly PSL enriched) 'assert's
being a legal construct in an entity that would be a Really Cool
Thing(tm).
The way I see it (I am on that committee) is that VHDL200x will integrate PSL
into VHDL
without having the comments. I don't believe that the PSL used in the VHDL200x
will be any (or that much) different than the latest version of PSL, at the
time VHDL200x is released for approval.
However, when will VHDL200x be approved? When will vendors fully suppport it?
This may be years from now.
Just because it's being done that way doesn't make it better. Designs
(including their entity) are usually better suited for reuse than a
testbench. So shipping the design with embedded protocol checker means
a less cluttered testbench and immediate availability of essential
verification code.
There is something positive to be said about having separate engineers work on
verification, including protocol checking, thatn on the RTL design. Thus
having verification done in testbench environment is good. I also like
embedded assertions (more easily expressed in PSL) because they can document
the design, and can detect errors closer the source (whitebox verification).
For testbench and protocol checks, I prefer seeing an external module (or
testbench) that uses PSL. That model shold be written by a separate
verification engineer.
Are you surprised? Am working on a second edition of current book to be
released next year.
PSL is pretty cool!
I agree and this is why I am looking forward to the VHDL-200x efforts
of integrating PSL into VHDL. Hopefully as a real language element,
rather that hiding it in comments.
You could also write separate vunits. Embedded assertion as comments is OK
though.
A PSL smart compiler recognized the PSL described as comments. No big deal!
This should not be a reason for not using PSL, and for salivating for
VHDL200x...
... your mouth would be dry by then...
Can you not have a passive process in the "statement part"?
I am not sure if you can write into variables of a process embedded in an
entity.
But you definitely cannot assign values onto signals local to an entity.
In most
cases PSL would of course be the more elegant way to describe
things. Just like in most cases textual regular expressions are more
elegant than coding the equivalent parser state machine by hand.
True
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ (e-mail address removed)
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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