VHDL language is out of date! Why? I will explain.

[Jan Decaluwe]

The Motto of MyHDL Project says: "From Python to silicon". Many people
are interested to see any clear example of how one can produce a bit
file for a FPGA from MyHDL.

For example, it could be an example of binding MyHDL with popular XST,
demonstrating, say, simple UART/VGA/LED/ or even SRAM controller. At
the same time, VHDL analogous program should be available for the
comparison.

Has been done, with an example from Xilinx itself:

http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

In that case, people can compare two digital design flows, executed
using different languages. Results will show the quality of
synthesized code, expended translation/synthesis time, and maybe will
reveal some difficulties.

Note that for synthesis, MyHDL *relies* on a Verilog/VHDL design flow.
Synthesis results will thus be similar, obviously.

Jan

 

[MikeShepherd564]

I am proponent of Open Source ideology, you know it, and

I do I believe that egoistic actions stops real progress in the
science, in the industry, in the society,
it stops to bring new knowledge to others.

Don't propound. We're just artisans here, not philosophers. We all
have notions of how certain things might be done better, but this
group is for practical problems, not for changing the world.