VHDL mailboxes

Discussion in 'VHDL' started by Verification Consultant, Aug 23, 2006.

  1. Hello!

    I am starting a new System Verification approach,
    and have found mailboxes to be the
    best implementation for my problem.
    The issue is that VHDL doesn´t have any such
    construct as SystemVerilog. Do you know of any
    VHDL implementation that could be used ?

    Best thanks,

    Fran.
    Verification Consultant, Aug 23, 2006
    #1
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  2. Verification Consultant wrote:

    > I am starting a new System Verification approach,
    > and have found mailboxes to be the
    > best implementation for my problem.
    > The issue is that VHDL doesn´t have any such
    > construct as SystemVerilog. Do you know of any
    > VHDL implementation that could be used ?



    VHDL has nothing like that built-in, but it does
    allow you build any sort of buffering
    you like for simulation using
    access types and protected types.

    -- Mike Treseler
    Mike Treseler, Aug 23, 2006
    #2
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  3. Verification Consultant

    Reuven Guest

    I've implemented mailboxes using linked lists in VHDL and the method
    has worked well for me in several testbenches. Look at Dr. Ashenden's
    book for some code.


    Verification Consultant wrote:
    > Hello!
    >
    > I am starting a new System Verification approach,
    > and have found mailboxes to be the
    > best implementation for my problem.
    > The issue is that VHDL doesn´t have any such
    > construct as SystemVerilog. Do you know of any
    > VHDL implementation that could be used ?
    >
    > Best thanks,
    >
    > Fran.
    Reuven, Aug 23, 2006
    #3
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