VHDL Model for a MIPS Processor

Discussion in 'VHDL' started by jdavis7667@gmail.com, May 4, 2013.

  1. Guest

    If anyone is able to do the following for me, it would be appreciated. Please comment the code, since I am trying to learn how to do code in VHDL for the future.

    1.Develop a VHDL model for the MIPS processor. The model should simulate a 4-stage (Fetch, Decode, Execute, and Write-back) pipeline design.
    2.The instruction memory should be modeled as a ROM, which can be part of the Fetch unit.
    3.The data memory should be modeled as a read/write Random Access Memory, which can be included within the Write-back stage.
    4.The register file should be modeled as a 3-port, 32 word, Random Access Memory, which can be included within the Decode unit.
    5.It should be assumed that all RAW data hazards will be handled using data forwarding between the Execute state and the Decode stage.
    6.Branch hazards should be resolved statically, i.e. assume that branch delay slots are filled either with a valid instruction or with nops.
    7.Implement the following R format instructions: jr, add, sub, and, or, slt, lw, sw, sb
    8.Implement the following I format instructions: beq, bne lbu, addi, subi
    9.Implement the following J format instructions: jal, j and nop.
    , May 4, 2013
    #1
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  2. Andy Guest

    Who is your professor, so I can forward it directly to him/her to save you the trouble?

    Andy
    Andy, May 6, 2013
    #2
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