vhdl model length of wire with delay ?

Discussion in 'VHDL' started by Tony Benham, Jun 24, 2005.

  1. Tony Benham

    Tony Benham Guest

    Hi,
    I'm trying to connect the bidirectional databuses of two models together,
    and create a delay in the path between them for a testbench. So in effect I
    need a piece of wire with a delay that will connect two bidirectional
    signals. So if neither bus is driving both ends of the 'wire' would be
    tristate, but if either end drives the signal it should be delayed at the
    other end of the 'wire', and driven.
    I cannot see how to model this at the moment. Can anyone suggest a way of
    doing this ?
    Regards
    Tony
    Tony Benham, Jun 24, 2005
    #1
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  2. On Fri, 24 Jun 2005 13:31:32 GMT, "Tony Benham"
    <> wrote:

    >I'm trying to connect the bidirectional databuses of two models together,
    >and create a delay in the path between them for a testbench. So in effect I
    >need a piece of wire with a delay that will connect two bidirectional
    >signals. So if neither bus is driving both ends of the 'wire' would be
    >tristate, but if either end drives the signal it should be delayed at the
    >other end of the 'wire', and driven.
    >I cannot see how to model this at the moment. Can anyone suggest a way of
    >doing this ?


    It's hard, and a weakness of VHDL that it can't easily model such
    things.

    If you can, by any means at all, split the wire into two
    unidirectional pieces, then it is easy. It's worth almost
    any amount of effort to do that.

    If you really, really can't do that, then there are some tricks
    to play that will work in some special cases. For example, if
    each bit of your wire is only ever driven with '0', '1', 'X' or
    'Z', you can abuse the weak-value states 'H', 'L' and 'W' to
    get something like the desired effect. But it's VERY tricky,
    especially if either end of the bus has more than one driver
    on it.

    It's depressingly easy in Verilog: just annotate the wire's
    declaration with a delay value.

    Ben Cohen's website has a zero-delay bidirectional wire model.
    It has some limitations, but it's a lot better than nothing
    and you may be able to hack it to add a delay.

    Finally, another possible approach is to modify each driver
    on the wire so that it implements the delay *in the driver*.
    This is messy because you must modify several bits of code,
    but it's easy to understand and it's sure to work.

    Good luck
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
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    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jun 24, 2005
    #2
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