VHDL newbie question about wires???

[coxsterdillon]

Hi,

I've just started using Xilinx ISE 7.1i and ModelSim (trial license).
I've seen some samples and created a few 7400 logic gates which compile
and I've seen waveforms of the various I/O.

I've can not get my head around wires and drivers. For example how
does one connect three devices together which bidirectional? I mean
say 3 74hc245's? On a drawing I'd just connect the buses together and
come up with combinational logic for the output enable (G) lines and
direction lines.

A -----------o--------------B
|
|
C

The only way I could come up with is a switch statement with lots of
assigns like
A <= B
A <= C
B <= A
B <= C
C <= A
C <= B

GD

 

[radarman]

Depends on the part, though most synthesis tools will correctly map to
LUTS if the part doesn't support true internal tri-states.

Try:

Ts_Out <= Sig_A when Ctrl_A = '1' else 'Z';
Ts_Out <= Sig_B when Ctrl_B = '1' else 'Z';
Ts_Out <= Sig_C when Ctrl_B = '1' else 'Z';

Make sure you pull up (or pulldown) the output at some point:
Ts_Out <= 'H';

Note, you may have to add an attribute to Ts_Out to get the tristate
pullup/pulldown, in which case you would need to add -- synthesis
translate_off/translate_on statements around the pullup model.

For parts that do support internal tristates, like the Xilinx XC4000
series, this will work just like it appears. On more modern
architectures, that don't support internal tri-states, the synthesizer
will silently replace the whole structure with muxes - or, pretty much
what you described.

BTW - if you know your target part doesn't support internal tri-states
(and most modern parts don't) study how you would solve the problem
with muxes - since that is what the synthesizer will do for you anyway.
This way, your code will be more clear (or at least closer to what is
actually generated in hardware)

It also pays to study the datasheet for the device you are targetting.

 

[Peter]

(e-mail address removed) skrev:

Hi,

I've just started using Xilinx ISE 7.1i and ModelSim (trial license).
I've seen some samples and created a few 7400 logic gates which compile
and I've seen waveforms of the various I/O.

Hi,

Forget everything about 7400 gates and start think functions. Try to
concentrate on what you want to create, instead of what was available
in the past. You will not see any benefit in VHDL if you hold on to
whats in the 7400 databook. Using small building blocks you get a big
overhead in component declarations, instatiations and wires. What you
can create with 7400 building blocks on one or two pages can often be
described with 5-10 lines of VHDL.
Tristate buses cant be used in programmable logic. Instead you must use
multiplexer structures.

Regards, Peter

 

[Duane Clark]

...
Tristate buses cant be used in programmable logic. Instead you must use
multiplexer structures.

I believe the various XC4000 families of Xilinx FPGAs had true tristate
internal buses. The synthesis tools I am aware of (XST and Synplify)
will correctly handle VHDL code for internal tristate buses in all newer
Xilinx FPGAs, too. Of course, it will physically be implemented with
multiplexers.

So maybe it would be preferable if programming FPGA internal logic to go
ahead and use multiplexers, but I think "must" might be a bit strong
Anyway, it wasn't clear to me the OP was talking about using them inside
an FPGA. Tristate buses are used all the time in testbenches, so he
would need to now how to write them for that case.

 

[Mike Treseler]

I've just started using Xilinx ISE 7.1i and ModelSim (trial license).
I've seen some samples and created a few 7400 logic gates which compile
and I've seen waveforms of the various I/O.
I've can not get my head around wires and drivers.

It is possible to create a design entity
at the wire and multiplexer level using vhdl,
as others have explained.

I find it more efficient to describe only
how the output ports are to be updated
at each clock tick, and leave the details
up to synthesis. For example, this netlist:

http://home.comcast.net/~mike_treseler/uart.pdf

includes over 50 muxes and hundreds of wires,
but few of these structures are specifically
described in the design entity source here:

http://home.comcast.net/~mike_treseler/uart.vhd


-- Mike Treseler

 

[Peter]

Tristate buses are used all the time in testbenches, so he

would need to now how to write them for that case.

Agreed!

/Peter