VHDL Novice - Error in code

Discussion in 'VHDL' started by Shar_ja, Jan 31, 2011.

  1. Shar_ja

    Shar_ja

    Joined:
    Jan 31, 2011
    Messages:
    2
    Hi all,

    I compiled a code and I'm getting an error that I just can't figure out after reading and searching to try and understand the signal statement to find what's wrong.

    Here's the part of the code that the compiler has a problem with:

    signal pulse: bit;
    signal Q: std_logic_vector (3 downto 0);


    The compiler highlights "signal" in the first line and says it's "Not a concurrent statement."


    If you need more of the code to understand what's happening before and after, please let me know and I'll get that on here asap.

    Thanks much!
    Shar_ja, Jan 31, 2011
    #1
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  2. Shar_ja

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Not a Concurrent Statement

    You need to show more code. The two statements are correct if they are in the proper context, but since you are getting an error they are being used in place in the code where they don't belong.
    eliascm, Jan 31, 2011
    #2
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  3. Shar_ja

    Shar_ja

    Joined:
    Jan 31, 2011
    Messages:
    2
    This is what the program should be doing on a CPLD board:

    -Turn on an LED for 5 seconds when one of the push-buttons is pressed.
    -The debounced counter will increment one count when another of the momentary push-button switches is pressed.


    Below is the entire code:


    library ieee;
    use ieee.std_logic_1164.all;

    entity TimerCounter is

    port (CLK0: in std_logic; PBTime: in std_logic; PBCount: in std_logic;
    TimerOut: out std_logic; SevenSegment:eek:ut std_logic_vector (0 to 6));

    attribute LOC: string;
    attribute LOC of CLK0: signal is "P11";
    attribute LOC of PBTime: signal is "P43";
    attribute LOC of PBCount: signal is "P31";
    attribute LOC of TimerOut: signal is "P02";
    attribute LOC of SevenSegment: signal is "P36 P37 P38 P39 P40 P41 P42";

    end entity TimerCounter;


    architecture TimerCounter_arch of TimerCounter is

    signal pulse: bit;
    signal Q: std_logic_vector (3 downto 0);


    begin
    Timer:process (PBTime,CLK0)
    variable cnt: unsigned (5 downto 0);
    begin
    if CLK0='1' and CLK0' event then
    if PBTime = '0' then cnt:= "000000"; TimerOut <= '0';
    elsif cnt = 40 then TimerOut <= '1';
    else cnt := cnt + "000001";
    end if;
    end if;
    end process;


    Debounce:process (PBCount,CLK0)
    variable cnt: unsigned (2 downto 0);
    begin
    if CLK0='1' and CLK0'event then
    if PBCount = '1' then cnt:= "000"; pulse <= '0';
    elsif cnt = 1 then pulse <= '1';
    else cnt:= cnt + "001";
    end if;
    end if;
    end process;


    Count: process (pulse)
    begin
    if pulse='1' and pulse' event then
    case Q is when "0000" => Q <="0001"; --1
    when "0001" => Q <="0010"; --2
    when "0010" => Q <="0011"; --3
    when "0011" => Q <="0100"; --4
    when "0100" => Q <="0101"; --5
    when "0101" => Q <="0110"; --6
    when "0110" => Q <="0111"; --7
    when "0111" => Q <="1000"; --8
    when "1000" => Q <="1001"; --9
    when "1001" => Q <="0000"; --0

    when others => Q <= "0000"; --default
    end case;
    end if;
    end process;


    Display: process(SevenSegment)
    begin
    if Q = "0000" then SevenSegment <= "0000001"; --0
    elsif Q = "0001" then SevenSegment <= "1001111"; --1
    elsif Q = "0010" then SevenSegment <= "0010010"; --2
    elsif Q = "0011" then SevenSegment <= "0000110"; --3
    elsif Q = "0100" then SevenSegment <= "1001100"; --4
    elsif Q = "0101" then SevenSegment <= "0100100"; --5
    elsif Q = "0110" then SevenSegment <= "0100000"; --6
    elsif Q = "0111" then SevenSegment <= "0001111"; --7
    elsif Q = "1000" then SevenSegment <= "0000000"; --8
    elsif Q = "1001" then SevenSegment <= "0000100"; --9

    else SevenSegment <= "0000001"; --default
    end process;


    end TimerCounter_arch;
    Shar_ja, Feb 2, 2011
    #3
  4. Shar_ja

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Using ghdl, I first get:
    So insert the missing 'end if' line there

    Then a few other errors show up:
    Adding
    use ieee.Numeric_STD.all;
    and replacing 'SevenSegment' with 'Q' in the sensitivity list,
    gets rid of all the errors.
    joris, Feb 3, 2011
    #4
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