VHDL novice question

[ra]

Hi,
I'm trying to define a component whose number of input ports, as well as
the size of the ports depend on a generic parameter. I was hoping to use
the following syntax:

entity mycomponent is
generic (
NUM_INPUTS : integer := 4;
DATA_WIDTH : integer := 32;
);
port(
CLK : in std_logic;
RESET : in std_logic;
A : array(0 to NUM_INPUTS-1) of std_logic_vector(0 to
DATA_WIDTH-1);
end mycomponent;

But modelsim doesn't seem to like this. I tried also

entity mycomponent is
generic (
NUM_INPUTS : integer := 4;
DATA_WIDTH : integer := 32;
);
port(
CLK : in std_logic;
RESET : in std_logic;
A : array(natural range 0 to NUM_INPUTS-1) of
std_logic_vector(0 to DATA_WIDTH-1);
end mycomponent;


Which didn't work either. As modelSim always complain with the message:

Error: mycomponent.vhd(61): near "array": expecting: STRING IDENTIFIER

I'm starting to think that I can't use array in the port declaration,
and I need to declare a type. However, because I'm using the type in the
ports, I need to do that in a package (which is kind of annoying).
Anyway, I tried that, defining the package as follows:


package my_util is

type std_logic_arr is array(natural range <>) of std_logic;
type std_logic_vector_arr is array(natural range <>) of
std_logic_vector(natural range <>);

end my_util;


But that didn't work either.

Can anybody suggest how to do this, possibly without requiring a package?


Thanks,
Roberto

 

[ra]

I found a thread on google news that seem to suggest that this is
impossible... just because of a crappy syntactic definition of VHDL.
please tell me it's not true. If it is, has anybody found a workaround?

Roberto

 

[Jim Lewis]

Roberto,
Bad news. Can't do it now.

Good news. It is a candidate for the next language rev. See:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

It is proposal # FT14

Cheers,
Jim

I found a thread on google news that seem to suggest that this is
impossible... just because of a crappy syntactic definition of VHDL.
please tell me it's not true. If it is, has anybody found a workaround?

Roberto

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[ra]

Ok. Now I know I'm not the first one getting into this mess, so I was
wondering what alternatives people have used. I can think about two, but
I need comments:

1) Use matrixes instead of array of vectors. This appears to work, but
there is a problem. If my components ports are now NxM wires (instead of
N ports each one being a std_logic_vector of size M), when I connect
ports I need to write a bunch of loops. Annoying.

2) This may be a stretch, but.... what if I declare the port width to be
fixed with some upper bound (let's say 32)? Then a port declaration
would be an array of bounded std_logic vectors. If then in the
architecture of the component I use my genric parameter DATA_WIDTH as
limit for loops to operate on signals, and therefore never operate on
the bits from DATA_WIDTH to 31, would simulation/synthesis get rid of
them as if they were not there in the first place?

Roberto

 

[ra]

BTW, is this any better in verilog?

Roberto

Roberto,
Bad news. Can't do it now.

Good news. It is a candidate for the next language rev. See:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

It is proposal # FT14

Cheers,
Jim

 

[Jim Lewis]

Roberto,
All matricies can be vectorized, hence, I would try the following:

entity mycomponent is
generic (
NUM_INPUTS : integer := 4;
DATA_WIDTH : integer := 32;
);
port(
CLK : in std_logic;
RESET : in std_logic;
A : std_logic_vector(0 to NUM_INPUTS*DATA_WIDTH-1);

end mycomponent;

Cheers,
Jim

Ok. Now I know I'm not the first one getting into this mess, so I was
wondering what alternatives people have used. I can think about two, but
I need comments:

1) Use matrixes instead of array of vectors. This appears to work, but
there is a problem. If my components ports are now NxM wires (instead of
N ports each one being a std_logic_vector of size M), when I connect
ports I need to write a bunch of loops. Annoying.

2) This may be a stretch, but.... what if I declare the port width to be
fixed with some upper bound (let's say 32)? Then a port declaration
would be an array of bounded std_logic vectors. If then in the
architecture of the component I use my genric parameter DATA_WIDTH as
limit for loops to operate on signals, and therefore never operate on
the bits from DATA_WIDTH to 31, would simulation/synthesis get rid of
them as if they were not there in the first place?

Roberto

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Allan Herriman]

BTW, is this any better in verilog?

Roberto

Worse

Allan.