VHDL oddity

Discussion in 'VHDL' started by Alex, Sep 19, 2006.

  1. Alex

    Alex Guest

    I would greatly appreciate if someone could explain the behavior I'm
    seeing for me.

    In the inner most if-state, where I write to bDATA_OUT ---- if I run
    the program as written, it does nothing (my DATA_OUT lines remain in
    the state they were previously). If I remove the "else, bDATA_OUT <=
    "11000000"" segment, it properly outputs 00001010. I don't understand
    why it would work w/o the else, but not w/.

    This is a snippet of a larger VHDL, trimmed down for debugging.

    Thank you.

    Alex McHale




    entity driver is
    Port ( CLOCK : in STD_LOGIC;
    ACTIVE : in STD_LOGIC;
    CLOCK_IN : in STD_LOGIC;
    LATCH_IN : in STD_LOGIC;
    DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
    ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0);
    DATA_CLOCK_OUT : out STD_LOGIC;
    CLOCK_OUT : out STD_LOGIC;
    LATCH_OUT : out STD_LOGIC;
    DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) );
    end driver;


    architecture Behavioral of driver is
    signal mode : STD_LOGIC := '0';
    signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000";
    signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0);
    begin
    process( CLOCK )
    begin
    if( rising_edge( CLOCK ) ) then
    if mode='0' then
    CLOCK_OUT <= '0';
    LATCH_OUT <= '0';

    mode <= '1';
    elsif mode='1' then -- DATA INCOMING
    if column_out(0)='0' then
    bDATA_OUT <= "00001010";
    else
    bDATA_OUT <= "11000000";
    end if;

    CLOCK_OUT <= '1';
    LATCH_OUT <= '1';
    column_out <= column_out + 1;

    mode <= '0';
    end if;
    end if;
    end process;

    DATA_OUT <= bDATA_OUT;
    end Behavioral;
    Alex, Sep 19, 2006
    #1
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  2. Alex

    smithodude Guest

    I'm having a quick guess now as I won't have access to any simulation
    tools until tomorrow...

    Take your assignation of 'mode' outside of the process. You're trying
    to assign 'mode' a value AND test its state with an IF statement.

    Mode is just going 0..1..0..1..0..1 on each clock edge I think so
    generate a separate process to do just that, something like....

    --------------------------------
    process(clock)
    begin

    if rising_edge(clock) then
    mode <= NOT mode;
    end if;
    end process;
    -------------------------------

    And remove the lines in your VHDL process that read:
    "mode <= '1';"
    and
    "mode <= '0';"

    DISCLAIMER...this might be wrong but like I say I haven't got any VHDL
    tools right now to simulate with

    Good luck
    Matt
    smithodude, Sep 20, 2006
    #2
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  3. Alex

    smithodude Guest

    OK, compiling and simulating this on Modelsim 5.6a and the design seems
    to work - DATA_OUT toggles between the two values.

    I did however need to change the 'column_out+1' line because the code
    is trying to add an integer to a std_Logic_vector

    column_out <=
    std_logic_vector(to_unsigned((to_integer(unsigned(column_out)) +
    1),10));


    This is a long winded way of adding 1 to a std_logic_vector and I'm
    sure someone else may have a better more concise way.

    Hope this works
    Matt
    smithodude, Sep 21, 2006
    #3
  4. what about this:

    column_out <= column_out + '1';

    adding the ieee.std_logic_arith.all package?

    smithodude wrote:
    > OK, compiling and simulating this on Modelsim 5.6a and the design seems
    > to work - DATA_OUT toggles between the two values.
    >
    > I did however need to change the 'column_out+1' line because the code
    > is trying to add an integer to a std_Logic_vector
    >
    > column_out <=
    > std_logic_vector(to_unsigned((to_integer(unsigned(column_out)) +
    > 1),10));
    >
    >
    > This is a long winded way of adding 1 to a std_logic_vector and I'm
    > sure someone else may have a better more concise way.
    >
    > Hope this works
    > Matt
    >
    alessandro basili, Sep 21, 2006
    #4
  5. Sorry but I don't think there is a problem assigning mode and then
    checking it, it is pretty ok.

    smithodude wrote:
    > I'm having a quick guess now as I won't have access to any simulation
    > tools until tomorrow...
    >
    > Take your assignation of 'mode' outside of the process. You're trying
    > to assign 'mode' a value AND test its state with an IF statement.
    >
    > Mode is just going 0..1..0..1..0..1 on each clock edge I think so
    > generate a separate process to do just that, something like....
    >
    > --------------------------------
    > process(clock)
    > begin
    >
    > if rising_edge(clock) then
    > mode <= NOT mode;
    > end if;
    > end process;
    > -------------------------------
    >
    > And remove the lines in your VHDL process that read:
    > "mode <= '1';"
    > and
    > "mode <= '0';"
    >
    > DISCLAIMER...this might be wrong but like I say I haven't got any VHDL
    > tools right now to simulate with
    >
    > Good luck
    > Matt
    >
    alessandro basili, Sep 21, 2006
    #5
  6. Alex

    David Ashley Guest

    smithodude wrote:
    > OK, compiling and simulating this on Modelsim 5.6a and the design seems
    > to work - DATA_OUT toggles between the two values.
    >
    > I did however need to change the 'column_out+1' line because the code
    > is trying to add an integer to a std_Logic_vector
    >
    > column_out <=
    > std_logic_vector(to_unsigned((to_integer(unsigned(column_out)) +
    > 1),10));
    >
    >
    > This is a long winded way of adding 1 to a std_logic_vector and I'm
    > sure someone else may have a better more concise way.
    >
    > Hope this works
    > Matt
    >


    Use unsigned instead of std_logic_vector for internal logic
    and include ieee.numeric_std.all
    for new designs. Convert to std_logic_vector in
    your port/interface for compatability.

    -Dave

    --
    David Ashley http://www.xdr.com/dash
    Embedded linux, device drivers, system architecture
    David Ashley, Sep 21, 2006
    #6
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