VHDL Operator associativity (Quartus II VHDL parser bug?)

[fons]

I am working on a compiler which generates VHDL and uses precedence and associativity to generate the least parenthesis possible.

According to VHDL for Engineers (http://books.google.com/books?id=7GKpXrMuZTIC&dq), this too expressions are equivalent:

a and not b or not a and b

((a and (not b)) or (not a)) and b

However, while Quartus II and Simulink accept the second one, they raise a parser error on the first one.

If the or is changed with and the expression doens't cause any problems:

a and not b and not a and b

Can anyone confirm wither is a bug or the book is wrong?

Thanks.