VHDL - '+' operator Usage

Discussion in 'VHDL' started by deena102, Feb 22, 2009.

  1. deena102

    deena102

    Joined:
    Feb 22, 2009
    Messages:
    4
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity Vedic4m is
    port(a : in unsigned(3 downto 0);
    b : in unsigned(3 downto 0);
    prod : out unsigned(7 downto 0));
    end Vedic4m;

    architecture behv of Vedic4m is

    signal p0 : unsigned(1 downto 0);
    signal p1, p6 : unsigned(1 downto 0);
    signal p2, p3, p4, p5 : unsigned(2 downto 0);

    begin
    p0 <= a(0) + b(0);
    p1 <= (a(1) and b(0)) + (a(0) and b(1)) + p0(1);
    p2 <= (a(2) and b(0)) + (a(1) and b(1)) + (a(0) and b(2)) + p1(1);
    p3 <= (a(3) and b(0)) + (a(2) and b(1)) + (a(1) and b(2)) + (a(0) and b(3)) + p2(2 downto 1);
    p4 <= (a(3) and b(1)) + (a(2) and b(2)) + (a(1) and b(3)) + p3(2 downto 1);
    p5 <= (a(3) and b(2)) + (a(2) and b(3)) + p4(2 downto 1);
    p6 <= (a(3) and b(3)) + p5(2 downto 1);

    prod <= p6 & p5 & p4 & p3 & p2 & p1 & p0;
    end behv;

    this is my code............

    I want to use the + operator to add the Bits ans Words as shown

    The error says

    # ERROR: C:/Modeltech_ae/examples/Vedic4(20): No feasible entries for infix op: "+"
    # ERROR: C:/Modeltech_ae/examples/Vedic4(20): Type error resolving infix expression.
    # ERROR: C:/Modeltech_ae/examples/Vedic4(21): No feasible entries for infix op: "+"
    # ERROR: C:/Modeltech_ae/examples/Vedic4(21): Bad expression.

    Can't I use the + operator this way??

    Please help
     
    deena102, Feb 22, 2009
    #1
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  2. deena102

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    The problem is that a(0) or p0(1) are of type std_logic, and adding std_logic with something else is not allowed.

    You can get around that using these helper functions:
    Code:
    function"+"(x,y : std_logic) return unsigned is
      begin
        return unsigned'('0' & x) + unsigned'('0' & y);
      end;
      
      function"+"(x : unsigned; y : std_logic) return unsigned is
      begin
        return x + unsigned'('0' & y);
      end;
    
      function"+"(x : std_logic; y : unsigned) return unsigned is
      begin
        return unsigned'('0' & x) + y;
      end;
    Oh, and then you end up with one more error that you need to ensure that the prod calculation doesn't thave the right number of bits. An untested attempt at it: (it compiles, but functionality is untested)
    Code:
    prod <= p6(1 downto 0) & p5(0) & p4(0) & p3(0) & p2(0) & p1(0) & p0(0);
     
    joris, Feb 23, 2009
    #2
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