VHDL-problem with symmetrical frequency divider by 3

Discussion in 'VHDL' started by Winfried Salomon, Jan 18, 2005.

  1. Hello,

    I am a beginner in VHDL and use Xilinx ISE 6.103i. I tried to program a
    symmetrical frequency divider by 3 in VHDL, which exists as hardware
    tested schematic solution with 3 D-FFs. But the VHDL version doesn't
    work at all, only the behavioral simulation with ModelSim works right,
    but the post fit simulation and the hardware not at all. The chip is an
    CPLD XC9572-15PC84, an Webcase at Xilinx had not yet success. I attached
    the code in div3_vhdl.vhd, which is very short and easy to understand.
    Why does it not work? The generated circuit is not a synchronous clocked
    state machine, there are no memory elements at all like D-FFS and it has
    no input, so it must be totally wrong.

    To generalize the question, there must be triggered on both rising and
    falling edge of clock in one process. Is this possible in VHDL? I
    suppose not! But I cannot find in books that this is illegal. Can it be
    a compiler dependent problem? I use the XST, perhaps another can solve
    the problem? Where is the mistake? Many thanks in advance,

    Winfried


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity div3_vhdl is
    Port ( clock : in std_logic;
    q_out : out std_logic);
    end div3_vhdl;

    architecture Behavioral of div3_vhdl is
    begin


    process(clock)
    variable stat_count:integer range 0 to 6;

    begin

    --check Status-Counter
    if(stat_count >5) then
    stat_count:=0;
    end if; --counter

    --assign output
    if(stat_count < 3) then
    q_out <= '0';
    else
    q_out <= '1';
    end if;

    --increment Status-Counter
    stat_count := stat_count+1;

    end process;

    end Behavioral;
     
    Winfried Salomon, Jan 18, 2005
    #1
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  2. Winfried Salomon

    Guest

    You are trying to infer a FF that is sensetive to both the rising and
    falling edge - such a FF is (mostly) not synthesizeable.
    the Modelsim can simulate it however..

    In order to design such a divider you need to use two sets of FFs each
    sensetive to a different edge (rising / falling) and then
    combine their outputs (using combinatorical logic - probably an "and"
    gate) to get your divided clock.

    Regards, Moti.
     
    , Jan 18, 2005
    #2
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  3. Winfried Salomon

    Guest

    Hi Winfried,
    Just for the fun I made such a divider - Ii belive that it should be
    synthesizeable..
    it uses 6 FFs and I'm sure that a reduced version is possible to create
    but that's the first thing I thought about.
    I hope it will help.

    p.s - I needed the reset so I added it..



    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity div3_vhdl is
    Port ( clk : in std_logic;
    reset : in std_logic;
    q_out : out std_logic);
    end div3_vhdl;

    architecture Behavioral of div3_vhdl is

    signal rise,fall: std_logic;

    begin

    process(clk,reset)
    variable r_cnt : integer range 0 to 2;
    begin
    if reset = '1' then
    r_cnt := 0;
    rise <= '1';
    elsif clk'event and clk ='1' then
    if r_cnt = 2 then
    r_cnt := 0;
    rise <= not rise;
    else
    r_cnt := r_cnt + 1;
    end if;
    end if;
    end process;

    process(clk)
    variable f_cnt : integer range 0 to 2;
    begin
    if reset = '1' then
    f_cnt := 2;
    fall <= '1';
    elsif clk'event and clk ='0' then
    if f_cnt = 2 then
    f_cnt := 0;
    fall <= not fall;
    else
    f_cnt := f_cnt + 1;
    end if;
    end if;
    end process;

    q_out <= fall xnor rise;

    end Behavioral;
     
    , Jan 18, 2005
    #3
  4. Hi Moti,

    <> schrieb im Newsbeitrag
    news:...
    > You are trying to infer a FF that is sensetive to both the rising and
    > falling edge - such a FF is (mostly) not synthesizeable.
    > the Modelsim can simulate it however..
    >


    it seems to be so, but there is no error message, although the circuit
    synthezising process failes.

    > In order to design such a divider you need to use two sets of FFs each
    > sensetive to a different edge (rising / falling) and then
    > combine their outputs (using combinatorical logic - probably an "and"
    > gate) to get your divided clock.
    >
    > Regards, Moti.
    >


    Yes, I made this on paper by myself without computer, it needs 3 D-FFS, 2
    inverters and 1 and2, 1 clock is inverted, a very simple looking circuit and
    it works fine. So I must think, in VHDL is no symmetrical odd frequency
    divider possible, because in 1 process not on both edges can be triggered.

    regards, Winfried
     
    Winfried Salomon, Jan 19, 2005
    #4
  5. Hi Moti,

    <> schrieb im Newsbeitrag
    news:...
    > Hi Winfried,
    > Just for the fun I made such a divider - Ii belive that it should be
    > synthesizeable..
    > it uses 6 FFs and I'm sure that a reduced version is possible to create
    > but that's the first thing I thought about.
    > I hope it will help.
    >
    > p.s - I needed the reset so I added it..
    >
    >


    thanks, I tested your code and it is implementable. Now it seems to be
    almost shure, that in VHDL not on both edges can be triggered. But
    separating this into 2 processes makes it complicated, you must synchronize
    them. In your example you try to synchronize it with reset, i will think
    about self synchronizing.

    The synthezised circuit is much more complicated than the 'paper' version
    and I fear, that VHDL cannot find an optimized solution, because the
    programmer must set a precondition, which IMHO is a contradiction to the
    sense of VHDL. Since I looked in books and asked several people, also
    experts, it is strange that no one knows this drawback.

    In another (beginners) problem I had short time ago, I wanted to build an
    up-down counter with two independent clocks in 1 process. Why this is not
    possible is easier to understand, because no synchronous network is possible
    to do that. But with the divider by 3 it is possible and therefore not to
    understand.

    Regards, Winfried
     
    Winfried Salomon, Jan 19, 2005
    #5
  6. Winfried Salomon

    jtw Guest

    "Winfried Salomon" <> wrote in message
    news:csmnut$51e$01$-online.com...
    > Hi Moti,
    >
    > <> schrieb im Newsbeitrag
    > news:...
    >> You are trying to infer a FF that is sensetive to both the rising and
    >> falling edge - such a FF is (mostly) not synthesizeable.
    >> the Modelsim can simulate it however..
    >>

    >
    > it seems to be so, but there is no error message, although the circuit
    > synthezising process failes.
    >
    >> In order to design such a divider you need to use two sets of FFs each
    >> sensetive to a different edge (rising / falling) and then
    >> combine their outputs (using combinatorical logic - probably an "and"
    >> gate) to get your divided clock.
    >>
    >> Regards, Moti.
    >>

    >
    > Yes, I made this on paper by myself without computer, it needs 3 D-FFS, 2
    > inverters and 1 and2, 1 clock is inverted, a very simple looking circuit
    > and
    > it works fine. So I must think, in VHDL is no symmetrical odd frequency
    > divider possible, because in 1 process not on both edges can be triggered.
    >
    > regards, Winfried


    It isn't a VHDL issue; it's a tools and target device issue. As was
    previously mentioned, it can simulate fine, but not be synthesizable. If
    your target architecture supports flip-flops that clock on each edge, and if
    your synthesis tools support that architecture, then it would be
    synthesizable. There are many other (conceptually more complicated)
    structures/building blocks that VHDL can simulate; many times, however, you
    must instantiate the desired component (such as Xilinx's DCMs, certain DDR
    (hah! both edges of the clock) registers which are available in Virtex
    family devices.) In the past, you would have had to instantiate adders and
    multiplier, but today many tools will synthesize the behavioral code and
    infer the appropriate underlying architecture(s.) Maybe in another few
    revisions, some will support inferred DDR, but don't hold your breath; it's
    a specialized function, and not difficult to just instantiate. However,
    that complicates the question of portability.

    Jason
     
    jtw, Jan 20, 2005
    #6
  7. Hi Jason,

    "jtw" <wrightjt @hotmail.invalid> schrieb im Newsbeitrag
    news:ytGHd.12731$...
    >
    >
    > It isn't a VHDL issue; it's a tools and target device issue. As was
    > previously mentioned, it can simulate fine, but not be synthesizable. If
    > your target architecture supports flip-flops that clock on each edge, and

    if
    > your synthesis tools support that architecture, then it would be
    > synthesizable. There are many other (conceptually more complicated)


    I just changed the chip to Virtex XCV400HQ240-4 anf the result is even
    worse. The RTL-viewer shows only nonsense and as I understand, this is a pre
    optimized circuit, which will be further optimized and fitted into hardware.
    So IMHO the XST is not able to synthesize a logical circuit to divide
    symmetrical by 3. In this case only 1 clock input must be inverted and the
    XST does't find the solution. If VHDL has not that restriction, then the XST
    must have it.

    A hardware restriction is not to see as in GALs. In the GALs I used all
    clocks are connected, so you cannot invert one, but in FPGAs this is not so.

    > structures/building blocks that VHDL can simulate; many times, however,

    you
    > must instantiate the desired component (such as Xilinx's DCMs, certain DDR
    > (hah! both edges of the clock) registers which are available in Virtex


    I discussed with a collegue about DCM in Virtex, but this is not the same as
    the the divider I want. I'm not yet familiar with DCM, but I suppose it is
    not a digital circuit and has a lock in behavior like PLL.

    > family devices.) In the past, you would have had to instantiate adders

    and
    > multiplier, but today many tools will synthesize the behavioral code and
    > infer the appropriate underlying architecture(s.) Maybe in another few
    > revisions, some will support inferred DDR, but don't hold your breath;

    it's
    > a specialized function, and not difficult to just instantiate. However,
    > that complicates the question of portability.


    I don't know how to multiply in VHDL, there are also cores in core
    generator. But I'm not shure if my problem is the same as to implement a
    complex function. The XST does't recognize the formulation of the problem
    and totally failes in solution. This is not a function block but a way to
    synthesize. It were interesting if other sythesize tools then XST can solve
    this problem, but I have none.

    regards, Winfried
     
    Winfried Salomon, Jan 21, 2005
    #7
  8. On Fri, 21 Jan 2005 01:37:27 +0100, "Winfried Salomon"
    <> wrote:

    >Hi Jason,
    >
    >"jtw" <wrightjt @hotmail.invalid> schrieb im Newsbeitrag
    >news:ytGHd.12731$...
    >>
    >>
    >> It isn't a VHDL issue; it's a tools and target device issue. As was
    >> previously mentioned, it can simulate fine, but not be synthesizable. If
    >> your target architecture supports flip-flops that clock on each edge, and

    >if
    >> your synthesis tools support that architecture, then it would be
    >> synthesizable. There are many other (conceptually more complicated)

    >
    >I just changed the chip to Virtex XCV400HQ240-4 anf the result is even
    >worse. The RTL-viewer shows only nonsense and as I understand, this is a pre
    >optimized circuit, which will be further optimized and fitted into hardware.
    >So IMHO the XST is not able to synthesize a logical circuit to divide
    >symmetrical by 3. In this case only 1 clock input must be inverted and the
    >XST does't find the solution. If VHDL has not that restriction, then the XST
    >must have it.


    The restriction isn't in VHDL. It's not in XST either.

    XST is quite capable of synthesising divide by 3 counter with
    symetrical output, given appropriate source code.

    You should be trying to end up with the design presented in this
    Xilinx app note:
    http://www.xilinx.com/xcell/xl33/xl33_30.pdf

    Regards,
    Allan
     
    Allan Herriman, Jan 21, 2005
    #8
  9. Hi Allan,

    Allan Herriman wrote:

    >
    >The restriction isn't in VHDL. It's not in XST either.
    >
    >XST is quite capable of synthesising divide by 3 counter with
    >symetrical output, given appropriate source code.
    >
    >
    >

    ok, but the source code is in my first mail, you can simulate but not
    implement it.

    >You should be trying to end up with the design presented in this
    >Xilinx app note:
    >http://www.xilinx.com/xcell/xl33/xl33_30.pdf
    >
    >Regards,
    >Allan
    >
    >

    Thanks for your tip, I just tested it and it works. It's another
    approach with 2 D-FFs and 1 RS-FF, the expenditure is almost the same as
    with my approach with 3 D-FFs, but my solution is somewhat faster ;-).

    But ..... it's not the solution of the problem. Of course you can write
    a schematic circuit in VHDL an then it must work, only you must find the
    circuit yourself. I hoped that VHDL or the implementation tool can find
    this circuit, but it cannot.

    Since Xilinx application note also have only a schematic and no
    VHDL-code I'm almost shure, that this problem is not solvable. You
    cannot trigger on both edges of a signal in one process, although you
    can simulate it behavioral. I will pursue the suggestion with splitting
    up in 2 communicating processes triggered on rising and falling edges,
    this could be a workaround.

    Regards, Winfried
     
    Winfried Salomon, Jan 21, 2005
    #9
  10. Winfried Salomon wrote:

    > But ..... it's not the solution of the problem. Of course you can write
    > a schematic circuit in VHDL an then it must work, only you must find the
    > circuit yourself. I hoped that VHDL or the implementation tool can find
    > this circuit, but it cannot.


    You have to distinguish between VHDL as behavioral language, and RTL
    subset of VHDL that can be synthesized. To create good HW implementations
    VHDL must be written in a certain way that different tools recognize.
    The tool might create something out of behavioral code, but the
    end result can be horrible in terms of speed and area (or might not work
    in real world). Also there are quite big differences between tools.
    Tools like Synplify can process more complex structures compared to
    synopsys DC.

    VHDL or Verilog are not a magical bullet. State machines can be coded
    in such a cryptic way that the downstream tools won't see it as a state
    machine. And after that the implementation can be much slover because
    SM optimisation tehqniques could not be used. But it is usually just
    as easy to code the SMs using the normal way of 2 or 3 processes
    (on clocked process and 1-2 combinatiorial ones).

    Clock dividers are quite special blocks where the actual gate implementation is
    important. All chips I have seen have used manual instantiation of
    library cells in clock structures. Also those cells usually are manually
    placed quite often. For example to get accurate 50:50 clock manually placed
    buffers might be needed because 1->0, 0->1 transitioning can have different
    propagation times in gates (that is usually layout work tough).

    > Since Xilinx application note also have only a schematic and no
    > VHDL-code I'm almost shure, that this problem is not solvable. You
    > cannot trigger on both edges of a signal in one process, although you
    > can simulate it behavioral. I will pursue the suggestion with splitting


    Of course some tool might even support that. But triggering at both edges
    is quite rare in normal synchronous logic. It makes also STA etc. more
    difficult. It's easier to use the common style in coding.


    --Kim
     
    Kim Enkovaara, Jan 21, 2005
    #10
  11. Hello Kim,

    Kim Enkovaara wrote:

    [....]

    >
    >> Since Xilinx application note also have only a schematic and no
    >> VHDL-code I'm almost shure, that this problem is not solvable. You
    >> cannot trigger on both edges of a signal in one process, although you

    >
    > > can simulate it behavioral. I will pursue the suggestion with splitting

    >
    > Of course some tool might even support that. But triggering at both edges
    > is quite rare in normal synchronous logic. It makes also STA etc. more
    > difficult. It's easier to use the common style in coding.
    >
    >
    > --Kim


    what is STA? Shure, this divider by 3 is a training example for
    designing logic and learning VHDL. But we already needed a clock divider
    by 3 in System Generator, which generates it automatically, though I
    cannot recognize the structure of it.

    So thank you and the others for replying, I'll procceed with the
    simplified workaround, a counter which counts edges, rising or falling
    edges. If I fail, I will return back with this problem.

    Regards, Winfried
     
    Winfried Salomon, Jan 24, 2005
    #11
  12. Winfried Salomon wrote:

    > what is STA? Shure, this divider by 3 is a training example for


    Static Timing Analysis

    --Kim
     
    Kim Enkovaara, Jan 24, 2005
    #12
  13. Winfried Salomon

    tsachg

    Joined:
    Aug 29, 2007
    Messages:
    1
    please send us the clock divider by 3 block diagram or

    an explanation of the implementation as described earlier:
    3 DFF, 2 inverters, 1 and2.

    Thank you very much
    Tsach

     
    tsachg, Aug 29, 2007
    #13
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