VHDL process and function problem

Discussion in 'VHDL' started by alomar, Jul 27, 2009.

  1. alomar

    alomar Guest

    hi all,

    I have a vhdl process question. For a vector 'x', I want to derive its
    unary or-reduction value, so I just write the following codes.
    Strangely, it doesn't work. So I transformed it to a function version
    which is proved to be correct.
    My question is what is the difference between these two methods.
    Thanks for your answering.

    -----------------------------------------------------------------------
    signal x : std_logic_vector(10 downto 0);

    process(x)
    variable result : std_logic :='0';
    begin
    for i in x'RANGE loop
    result := result or x(i);
    end loop;
    or_reduce_x <= result;
    end process;
    -------------------------------------------------------------------------
     
    alomar, Jul 27, 2009
    #1
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  2. alomar wrote:
    > hi all,
    >
    > I have a vhdl process question. For a vector 'x', I want to derive its
    > unary or-reduction value, so I just write the following codes.
    > Strangely, it doesn't work. So I transformed it to a function version
    > which is proved to be correct.
    > My question is what is the difference between these two methods.
    > Thanks for your answering.
    >
    > -----------------------------------------------------------------------
    > signal x : std_logic_vector(10 downto 0);
    >
    > process(x)
    > variable result : std_logic :='0';
    > begin
    > for i in x'RANGE loop
    > result := result or x(i);
    > end loop;
    > or_reduce_x <= result;
    > end process;
    > -------------------------------------------------------------------------


    I expect you want a function, not a process, to form the value.
    Show the or_reduce_x declaration.
    What is driving X?

    -- Mike Treseler
     
    Mike Treseler, Jul 28, 2009
    #2
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  3. alomar

    alomar Guest

    On 7月28æ—¥, 上åˆ7時16分, Mike Treseler <> wrote:
    > alomar wrote:
    > > hi all,

    >
    > > I have a vhdl process question. For a vector 'x', I want to derive its
    > > unary or-reduction value, so I just write the following codes.
    > > Strangely, it doesn't work. So I transformed it to a function version
    > > which is proved to be correct.
    > > My question is what is the difference between these two methods.
    > > Thanks for your answering.

    >
    > > -----------------------------------------------------------------------
    > > signal x : std_logic_vector(10 downto 0);

    >
    > > process(x)
    > >     variable result : std_logic :='0';
    > > begin
    > >     for i in x'RANGE loop
    > >         result := result or x(i);
    > >     end loop;
    > >     or_reduce_x <= result;
    > > end process;
    > > -------------------------------------------------------------------------

    >
    > I expect you want a function, not a process, to form the value.
    > Show the or_reduce_x declaration.
    > What is driving X?
    >
    >    -- Mike Treseler



    Er... Actually, I have on idea what you mean. The vector 'x' is driven
    by some combinaional subcircuit and
    or_reduce_x is a signal of type std_logic

    signal or_reduce_x : std_logic;

    When I sim the process above, the or_reduce_x always has some
    miscellaneous value, such as 'X','U'...
    I just don't know why.
     
    alomar, Jul 28, 2009
    #3
  4. alomar wrote:
    > -----------------------------------------------------------------------
    > signal x : std_logic_vector(10 downto 0);
    >
    > process(x)
    > variable result : std_logic :='0';
    > begin
    > for i in x'RANGE loop
    > result := result or x(i);
    > end loop;
    > or_reduce_x <= result;
    > end process;
    > -------------------------------------------------------------------------


    The difference to the function variant

    function or_reduce (v : in std_ulogic_vector) return std_ulogic is
    variable result : std_ulogic := '0';
    begin
    for i in v'RANGE loop
    result := result or v(i);
    end loop;
    return result;
    end function or_reduce;

    is the initialization of the variable result. While result is
    initialized at every execution of the function, with the process variant
    it is only initialized at the first run of the process.

    Thus, with your process variant you accumulate all the previous values
    of result.

    Michael Roland
     
    Michael Roland, Jul 28, 2009
    #4
  5. alomar wrote:
    > -----------------------------------------------------------------------
    > signal x : std_logic_vector(10 downto 0);
    >
    > process(x)
    > variable result : std_logic :='0';
    > begin
    > for i in x'RANGE loop
    > result := result or x(i);
    > end loop;
    > or_reduce_x <= result;
    > end process;
    > -------------------------------------------------------------------------


    The difference to the function variant

    function or_reduce (v : in std_ulogic_vector) return std_ulogic is
    variable result : std_ulogic := '0';
    begin
    for i in v'RANGE loop
    result := result or v(i);
    end loop;
    return result;
    end function or_reduce;

    is the initialization of the variable result. While result is
    initialized at every execution of the function, with the process variant
    it is only initialized at the first run of the process.

    Thus, with your process variant you accumulate all the previous values
    of result.

    Michael Roland
     
    Michael Roland, Jul 28, 2009
    #5
  6. alomar

    Enes Erdin Guest

    On 28 Temmuz, 10:17, Michael Roland <> wrote:
    > alomar wrote:
    > > -----------------------------------------------------------------------
    > > signal x : std_logic_vector(10 downto 0);

    >
    > > process(x)
    > >     variable result : std_logic :='0';
    > > begin
    > >     for i in x'RANGE loop
    > >         result := result or x(i);
    > >     end loop;
    > >     or_reduce_x <= result;
    > > end process;
    > > -------------------------------------------------------------------------

    >
    > The difference to the function variant
    >
    >   function or_reduce (v : in std_ulogic_vector) return std_ulogic is
    >     variable result : std_ulogic := '0';
    >   begin
    >     for i in v'RANGE loop
    >       result := result or v(i);
    >     end loop;
    >     return result;
    >   end function or_reduce;
    >
    > is the initialization of the variable result. While result is
    > initialized at every execution of the function, with the process variant
    > it is only initialized at the first run of the process.
    >
    > Thus, with your process variant you accumulate all the previous values
    > of result.
    >
    > Michael Roland


    That is true. In the process form, trying this will hopefully fix the
    problem.

    -----------------------------------------------------------------------
    signal x : std_logic_vector(10 downto 0);

    process(x)
    variable result : std_logic :='0';
    begin
    result := x(0);--<--
    for i in x'RANGE loop
    result := result or x(i);
    end loop;
    or_reduce_x <= result;
    end process;
    -------------------------------------------------------------------------
     
    Enes Erdin, Jul 28, 2009
    #6
  7. alomar

    Andy Guest

    On Jul 28, 7:32 am, Enes Erdin <> wrote:
    >
    > That is true. In the process form, trying this will hopefully fix the
    > problem.
    >
    > -----------------------------------------------------------------------
    > signal x : std_logic_vector(10 downto 0);
    >
    > process(x)
    >     variable result : std_logic :='0';
    > begin
    >     result := x(0);--<--
    >     for i in x'RANGE loop
    >         result := result or x(i);
    >     end loop;
    >     or_reduce_x <= result;
    > end process;


    Note that this implementation, while logically correct in the final
    result, OR's X(0) twice. Furthermore, by specifically referencing X
    (0), it is dependent upon X'range being defined to include the index
    element 0, which might not be the case for all applications. Better to
    just initialize result to '0' instead.

    For reusability (i.e. the ability to include in a package) it is best
    if this is implemented as a function, even though the attempted
    implementation as a process does illuminate subtle differences between
    initializations in functions and processes.

    Whether implemented as an entity/architecture (with an unconstrained
    input port) or as a function, it is important to try to handle non-
    normal cases (such as vectors not defined with the usual "N downto 0"
    range) in reusable code. Sometimes declaring a local variable (or
    signal) with the range (x'length - 1 downto 0), and copying the input
    into it is required.

    Andy
     
    Andy, Jul 28, 2009
    #7
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