VHDL process synthesis problem

[xiheasas]

Hi all,
I played a trick on VHDL to understand better the synthesis of process statement. I set a same signal (clk) to both level-triggled and edge-triggled as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_device IS
PORT ( data : IN STD_LOGIC;
-- rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
outbuf : OUT STD_LOGIC);
END my_device;

ARCHITECTURE behavior OF my_device IS
BEGIN
PROCESS (clk)
BEGIN
IF (clk = '1') THEN
outbuf <= '0';
ELSIF (falling_edge(clk)) THEN
outbuf <= data;
END IF;
END PROCESS;
END behavior;

I expected the RTL would be a dffr of which the reset and clock port are bounded up together (clk), but synplify pro 9.6 translated this segment of code as shown in the attachment. Could there be someone to help me to go through this matter?
Thanks in advance.

 

[jeppe]

Hi

In general will this construction give you a lot of timing problems.
But try this code instead.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity my_source is
PORT (  data : IN STD_LOGIC;
      -- rst : IN STD_LOGIC;
         clk : IN STD_LOGIC;
      outbuf : OUT STD_LOGIC);
end my_source;

architecture Behavioral of my_source is
   signal Reset: STD_LOGIC;
begin
   Reset <= clk;

   PROCESS (clk,Reset)
   BEGIN
      IF (Reset = '1') THEN
         outbuf <= '0';
      ELSIF (falling_edge(clk)) THEN
         outbuf <= data;
      END IF;
   END PROCESS;

end Behavioral;

If you want to know more about VHDL / Processes then search the net
for the interactive book: EVITA VHDL

Your welcome

 

[xiheasas]

Thx, Jeppe. I would like to check for the document. Another question, why introducing a new signal will reduce the timing hazard? It would be better if you recommend some readings